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astei87
Adventurer
Adventurer
6,272 Views
Registered: ‎09-03-2015

Cannot see Debug cores

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Hello Guys,

 

i have a problem with debugging in Vivado. Normaly it works always, but in

the current project not. I have set like always my debug signals with "setup De Bug". 

After generating the bitstream, i open the hardware manager, flash the device but i don't see any

debug signals. I receive the following message:

 

warnung.JPG

 

When i open the implemented design, i see that the debug cores are placed in the device. I Also see the 

Schemetic:

u_ila.JPG

The Clock for the debug cores comes from the Processing System -> FCLK_CLK0. So it should be a free-running clock. 

Does anyone know what i did wrong? thanks

 

 

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balkris
Xilinx Employee
Xilinx Employee
11,373 Views
Registered: ‎08-01-2008

your project may got corrupted. I think you can try with new project

 

https://forums.xilinx.com/t5/Design-Tools-Others/ILA-core-not-recognized-by-hardware-manager/td-p/552554

https://forums.xilinx.com/t5/Design-Tools-Others/Hardware-Manager-finds-no-debug-cores/td-p/710113

https://forums.xilinx.com/t5/Debug-Tools/Hardware-Manager-error-relative-ila-ip-core-vivado-13-4/td-p/396319

 

check this guide as well

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

Thanks and Regards
Balkrishan
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3 Replies
balkris
Xilinx Employee
Xilinx Employee
11,374 Views
Registered: ‎08-01-2008

your project may got corrupted. I think you can try with new project

 

https://forums.xilinx.com/t5/Design-Tools-Others/ILA-core-not-recognized-by-hardware-manager/td-p/552554

https://forums.xilinx.com/t5/Design-Tools-Others/Hardware-Manager-finds-no-debug-cores/td-p/710113

https://forums.xilinx.com/t5/Debug-Tools/Hardware-Manager-error-relative-ila-ip-core-vivado-13-4/td-p/396319

 

check this guide as well

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Give kudos in case a post in case it guided to the solution.

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arpansur
Moderator
Moderator
6,257 Views
Registered: ‎07-01-2015

Hi @astei87,

 

Can you please try connecting system clock to ILA and implement the design again?

Let us know if the issue persists after connecting sys_clk.

Thanks,
Arpan
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astei87
Adventurer
Adventurer
6,237 Views
Registered: ‎09-03-2015

Thx for you help guys,

 

it seems that my design was somehow corrupted. I've built a new design and it works now. Thank you

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