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Visitor jcreighton
Visitor
344 Views
Registered: ‎06-06-2018

Changing clock buffer enable % does not change reported clock power?

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Using the Vivado power estimator, I've observed that changing the clock buffer enable % does not result in a change in the reported power, which I find confusing.

Here is an example of what I'm doing using a toy project in Vivado 2018.3. After place & route, I run the power estimator, and examine the power in the "Clocks" category:

xilinx1.png

"Clk200_gated" is driven by a BUFG with a clock enable. The enable % has been estimated by the vector-less propagation algorithm. I change the power properties of the net driving the clock enable of the relevant BUFG:

xilinx2.png

This results in the following TCL command being run:

set_switching_activity -toggle_rate 0.000000 -static_probability 1.000000 [get_nets vio_Clk200_buffer_enable]

After that, I rerun the power estimator:

xilinx3.png

The "Clock Buffer Enable (%)" has been updated according the to the switching activity that I set, but the reported power does not change.

Why is this? If the "Clocks" category of power consumption is supposed to reflect the power incurred by toggling the clock net, why doesn't changing the duty cycle change the reported power?

 

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Visitor jcreighton
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255 Views
Registered: ‎06-06-2018

Re: Changing clock buffer enable % does not change reported clock power?

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After discussing this with our Xilinx FAE, he suggested trying to run the text-mode power report rather than the GUI, and when I did so I saw the following message:

WARNING: [Power 33-410] BUFGCE_Clk200_gated : User defined Switching Activity setting is ignored on global clock buffers. Use set_case_analysis instead to constrain Clock Enable pin. Please ignore this message if desired set_case_analysis is already set.

When I use "set_case_analysis", I see a power delta as expected. So it seems that for global clock buffers, the switching activity is ignored for whatever reason, and "set_case_analysis" is the preferred tool.

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Visitor jcreighton
Visitor
256 Views
Registered: ‎06-06-2018

Re: Changing clock buffer enable % does not change reported clock power?

Jump to solution

After discussing this with our Xilinx FAE, he suggested trying to run the text-mode power report rather than the GUI, and when I did so I saw the following message:

WARNING: [Power 33-410] BUFGCE_Clk200_gated : User defined Switching Activity setting is ignored on global clock buffers. Use set_case_analysis instead to constrain Clock Enable pin. Please ignore this message if desired set_case_analysis is already set.

When I use "set_case_analysis", I see a power delta as expected. So it seems that for global clock buffers, the switching activity is ignored for whatever reason, and "set_case_analysis" is the preferred tool.