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Registered: ‎09-01-2009

ChipScope Triggering

Hi everyone, I'm new to Chipscope and have a (hopefully) simple problem that I can't figure out. I'm using Chipscope 9.2 to monitor a piece of IP but I need to be able to monitor it for a 'meaningful' timeframe (around 40ms). At the moment, I can only get the triggering towork when I sample on every clock tick, but as the system runs on a 24MHz clock, this gives a far shorter sampling window than needed.

Ideally, I want to set the triggering such that Chipscope only takes a sample every 64 clock ticks (say). If necessary, I can add a free-runing counter to the IP to help with this but I'm afraid I have no idea how to set up Chipscope properly to achieve the task.

Any help would be very appreciated,


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Xilinx Employee
Xilinx Employee
Registered: ‎01-03-2008

What you are looking to do isn't part of the features of the ILA core.


You suggestion to create a counter to be able to control this is right way to accomplish what you want to do.


If you only want to collect a sample every 64 clock cycles, then you can use a 6-bit counter to count from 0 to 63 and a comparator (either all zeros or all ones)  to generate the trigger signal to the ILA core.


Verilog example:

always @ (posedge clk)


   if (reset )

       count[5:0] <= 6'b00_0000;


       count[5:0] <= count[5:0] + 1'b1;



assign trigger_64 = (count[5:0] == 6'b00_0000);



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