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Visitor
Visitor
11,026 Views
Registered: ‎07-31-2014

ChipScope in PlanAhead has problem with routing

Hello,

 

this is my first design with a Spartan 6 device and PlanAhead 14.7.

I want to use the ChipScope logic analyzer with PlanAhead 14.7. After I marked some signals as debug signal in synthesized netlist view and I setup a chipscope I get the following error message:

 

ERROR: [Constraints 18-608] We cannot route the nets within the site OLOGIC_X0Y61. Reason: Conflicting nets for physical connection driven by OLOGIC_X0Y61.OSRUSED.OUT: i_cfgreg/i2c_slave_1/iReset_inv GROUND

Can you give me a hint to correct the problem?

 

Thank you for your help

 

best regards

martin sauer

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Xilinx Employee
Xilinx Employee
11,017 Views
Registered: ‎07-01-2010

Hi Martin,

Did you try commenting the constraints in the ucf and see if that allow to route the design completely?

This will allow us to know if the issue with constraints conflict etc.

Can you try commenting the constraints in the ucf and let me know if you are able route the design so that i can suggest you further?

Regards,
Achutha
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Visitor
Visitor
11,008 Views
Registered: ‎07-31-2014

Hi Achutha,

 

ok with an empty ucf file I can creat a debug core.

 

Attached you can find my UCF File.

 

 

best regards

martin

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Xilinx Employee
Xilinx Employee
11,004 Views
Registered: ‎07-01-2010

Hi Martin,

Did the empty ucf file helped you to complete route of your design?

Regards,
Achutha
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Visitor
Visitor
10,967 Views
Registered: ‎07-31-2014

Hi Achutha,

 

yes. With an empty ucf file it is possible to insert the chipscope core.

 

best regards

 

martin sauer

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