07-31-2014 08:49 AM
this is my first design with a Spartan 6 device and PlanAhead 14.7.
I want to use the ChipScope logic analyzer with PlanAhead 14.7. After I marked some signals as debug signal in synthesized netlist view and I setup a chipscope I get the following error message:
ERROR: [Constraints 18-608] We cannot route the nets within the site OLOGIC_X0Y61. Reason: Conflicting nets for physical connection driven by OLOGIC_X0Y61.OSRUSED.OUT: i_cfgreg/i2c_slave_1/iReset_inv GROUND
Can you give me a hint to correct the problem?
Thank you for your help
07-31-2014 11:57 AM
08-01-2014 12:27 AM
08-01-2014 02:45 AM
08-03-2014 10:35 PM
yes. With an empty ucf file it is possible to insert the chipscope core.