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ronnywebers
Advisor
Advisor
8,757 Views
Registered: ‎10-10-2014

[Chipscope 16-3] Cannot debug net 'u_ila_0_wea[0]'; it was auto-generated for ChipScope (99 more like this)

After synthesizing my block design with Zynq, some Xilinx IP and a custom IP, I marked several nets for debug (netlist window -> right click -> mark debug)

 

During implementation I get about 100 critical warnings, saying :

 

[Chipscope 16-3] Cannot debug net 'u_ila_0_wea[0]'; it was auto-generated for ChipScope.

 

anyone knows where this error comes from? 

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arpansur
Moderator
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Registered: ‎07-01-2015

Hi @ronnywebers,

 

Can you please verify if you have dbg_hub and ILA in the design?

 

Thanks,
Arpan

Thanks,
Arpan
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vsrunga
Xilinx Employee
Xilinx Employee
8,741 Views
Registered: ‎07-11-2011

@ronnywebers

 

Below links may give you a clue 

 

http://www.xilinx.com/support/answers/64735.html

 

https://forums.xilinx.com/t5/Advanced-Tool-Methodologies/Using-the-ILA-Core-to-monitor-Tri-Mode-Ethernet-MAC-GMII-signals/td-p/673569

 

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ronnywebers
Advisor
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Registered: ‎10-10-2014

hello @arpansur, if I enter 'get_debug_cores' 

 

returns : dbg_hub design_1_i/vio_0 u_ila_0_0

 

note that the VIO is instantiated in my block design.

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arpansur
Moderator
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8,726 Views
Registered: ‎07-01-2015

Hi @ronnywebers,

 

What is u_ila_0_0?

Is there ILA in the netlist window?

 

Thanks,
Arpan

Thanks,
Arpan
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