04-29-2016 03:10 AM
After synthesizing my block design with Zynq, some Xilinx IP and a custom IP, I marked several nets for debug (netlist window -> right click -> mark debug)
During implementation I get about 100 critical warnings, saying :
[Chipscope 16-3] Cannot debug net 'u_ila_0_wea'; it was auto-generated for ChipScope.
anyone knows where this error comes from?
04-29-2016 03:19 AM
Can you please verify if you have dbg_hub and ILA in the design?
04-29-2016 03:56 AM
Below links may give you a clue
04-29-2016 04:31 AM
hello @arpansur, if I enter 'get_debug_cores'
returns : dbg_hub design_1_i/vio_0 u_ila_0_0
note that the VIO is instantiated in my block design.
04-29-2016 06:00 AM
What is u_ila_0_0?
Is there ILA in the netlist window?