02-08-2016 04:19 PM
I recreated the memory controller interface for Virtex 5 board (XUPV5-LX110T) and added a chipcope ICON and ILA core. I have recreated the original tutorial and made sure that the design sources are exactly the same. I can generate the bit stream and dump it on the FPGA. Opening Chipscope, it can identify an ILA core. However, I cannot trigger the sampling as it looks like the ILA clock is not driven. I get the following message: " waiting for core to be armed, slow or stopped clock". The interesting thing is that the precompiled bitstream (from the tutorial) can be dumped on the FPGA and triggered. In other words, I can collect samples from the pre-compiled bit stream. I would like to know what could be the issue with my bitstream. I have tried the following things:
1. I tried to reuse the ucf files from the precompiled bit stream but I get a bunch of errors from the synthesis. The part that I can reuse is the IO standards. However, that does not help.
2. Tried inserting the ILA and ICON cores using both chipscope pro generator and insertor.
3. Tried to route different clock signals to the ILA clock port. Still cannot trigger the sampling.
Is there a way to check if the ILA core ports are connected. To this end, I have put in the
synthesis syn_black_box syn_noprune = 1
for the ILA and ICON cores.
Any suggestions will be helpful.
I am using Chipscope Pro 14.4 and Xilinx ISE 14.4.
02-08-2016 07:00 PM