04-27-2018 03:14 AM
I've been using the Chipscope component instantiation flow successfully for years...
However, the requirement to generate the ILA via IP catalog and instantiating it as part of the code may prove very time consuming for large designs.
Recently, I started to explore the "insertion flow". I tried using the "Mark Debug" TCL command on the exact names as in my HDL code. It worked for some signals - but not for all...Seems like the tool expects the Netlist name which doesn't necessarily match the net HDL name.
Is there a way to work around this?
04-30-2018 11:21 AM
If you already know which nets you will want to debug, you can use the mark_debug attribute into the HDL code already, so when you get to the synthesis part and start inserting the ILA using the "Setup Debug", all those marked nets will already be shown for you.
I understand that the net names might change, especially because Vivado may perform some optimizations during synthesis, which can get rid of some nets or rename them.
I'd recommend hitting Ctrl + F to open the Find wizard, and look for your net with the known name or part of it, using a *. Specially if it's a net deep several layers into the design, the initial names might get changed but the final name might be still preserved.
Another option, is to open the synthesized design, switch the layout to debug, and there you can visualize the schematics. You might be able to find the net you want, and then right-click on it and select "Mark Debug".
Please let us know if that helps.
05-17-2018 10:24 AM
Did you get the chance to fix the issue?
pleas let us know if it worked or if you still need support.