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Registered: ‎11-23-2018

Chipscope wrong data representation; Data changes without rising edge

I am running chipscope 14.4 with a capture clock at 60MHz on my Virtex 5 design done in ISE14.4. I've generated a 1MHz clock from the same 60 MHz base clock using counter. This 1MHz signal has been verified on oscilloscope also and works fine. I have an RS485 module based on this 1MHz clock. Inside the process I've made all logic based on rising edge of 1MHz clock. However when I'm debugging in chipscope I am seeing the registers changing along with inbound SPI data even in the absence of rising edge. Is this a representation issue with chipscope or can the signal really change without rising edge ?

ISP side SSTS SPI Link2.jpg
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