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Registered: ‎10-11-2013

Clarification on inserting debug cores in netlist insertion probing flow


I am using Synplify Premier and Vivado tools for synthesis and implementation of a design. For debugging with Logic Analyzer I'd like to add debug cores to the synthesized netlist so as to avoid re-running the synthesis. 


The programming and debugging section of Vivado Design Suite user guide specifies the ways of marking signals for debug in a synthesized netlist-based project. One of them is-

Using Synplify tool we can mark nets in HDL source with mark_debug and syn_keep constraints OR 

we can use mark_debug constraint alone in the SDC file.

The manual also says that synthesis of the design containing debug cores is required after marking nets.


I have a few questions about this-


1)   Where is the synthesized netlist used here if we are marking nets directly on the HDL source?

2)   When I synthesize the design after marking nets, is it the entire design that gets synthesized again or is it only the debug cores?

3)   If the entire design gets synthesized then what is the point in using a post-synthesized netlist?

4)   If I have to do away with re-synthesis of the design, should I use mark_debug constraint on the XDC file which I give as an input to Vivado for implementation? (without making any changes to the EDIF netlist)


Thank you

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