02-02-2019 09:59 PM - edited 02-02-2019 09:59 PM
Hello guys. For my project we are working on an encryption core. In the implementation part inorder to check proper functionality, i have used the VIO core. I am pretty much new to design so pardon me for any misunderstanding. I want to download the bitstream onto an FPGA and check functionality using VIO. I have specified a constraint file which only has the command to get the onboard clock and use in in the core. After implementation, i get the following critical warning.
What does this mean? There are no constraint files named xsdbm.xdc in my computer. Also I dont have a clear picture on how constraint files work and how to get proper timing and power reports for the entire design. Would be of much help if someone can help me out with where to start. Thanks in advance.
02-04-2019 10:11 AM
The first issues are happening already during synthesis. It's saying that the VIO probes are not connected to any logic.
You also cannot connect the VIO probes and clock via XDC commands, it has to be done in your top file in VHDL/Verilog.
The other xdc issues seems to be related to the dbg_hub, which is what connects the VIO to the whole JTAG communication. This is done automatically by Vivado, and since you are failing to correct implement the VIO, the dbg_hub issues might just be a consequence of that.
Please take a look and try to follow the instructions for implementing a VIO in the document Vivado Programming and Debugging - UG936 (v2018.3), Lab 3, pg. 28.
03-14-2019 08:11 AM
03-20-2019 03:20 AM