03-24-2010 09:31 PM
03-24-2010 11:12 PM
You can not connect the O of an OBUF, the I of an IBUF or the IO of an IOBUF to anything other than a top level port because these pins on the primitives represent the external device connection.
Instead you need to use the nets connected to the I of the OBUF, O of an IBUF or the T, O, I of IOBUF to the ChipScope ILA core.
03-25-2010 02:21 AM
Thanks for your reply. Yes that is what I am trying to do. This is what my code looks like
M1: MicroBlaze port map( uart_rx, uart_tx, leds, I2C_SCL, I2C_SDA, fpga_clock, fpga_reset_ex);
CS_ICON1: ChipScope_ICON port map(control_bus);
CS_ILA1: ChipScope_ILA port map(control_bus, fpga_clock, ILA_data, ILA_trig0);
I2C_SCL_IBUF: IBUF port map( I2C_SCL_I, I2C_SCL);
I2C_SDA_IBUF: IBUF port map( I2C_SDA_I, I2C_SDA);
I2C_SCL_OBUF: OBUF port map( I2C_SCL, I2C_SCL_O);
I2C_SDA_OBUF: OBUF port map( I2C_SDA, I2C_SDA_O);
ILA_data(0) <= I2C_SCL_I;
ILA_data(1) <= I2C_SDA_I;
ILA_data(2) <= I2C_SCL_O;
ILA_data(3) <= I2C_SDA_O;
This code is giving me the second error I mentioned before. Declaring IBUF and OBUF components for I2C signals in the code seems to cause problems because of the existing IBUF, OBUF and IOBUF components synthesized for the I2C signals by the ISE. Is there anyway I can use the signals from the IBUF and OBUF synthesized by ISE so that I don't have to instantiate IBUF and OBUF components?
03-25-2010 08:45 AM
A couple of things.
1) Instantiating modules without including the port names is a bad design practice as it relies about the ordering within the module definition to match the signals to the ports. Another designer looking at your code would have to have both the module and the instantiation viewable at the same time to determine if the connections are correct. Your code should look like this.
I2C_SCL_IBUF : IBUF port map (O=>I2C_SCL_I, I=>I2C_SCL);
2) I2C is a bi-directional bus the SCL and SDA need to either be the IO pin of an IOBUF or an IBUF/OBUFT combination.
3) Your MicroBlaze module must include all of the IO cells (and the IOBUF for the I2C interface), so in order to observe the signals you must insert the ILA core in the MicroBlaze module. I am not an EDK expert, but so I don't know if this is possible within EDK. If it isn't then you could use the ChipScope Core Inserter to add the ILA after synthesis or connect these 4 ILA data pins to another available signal and after the design has been placed and routed use FPGA Editor to reassign the ILA data pins to these locations.
The ChipScope User Guide should have all of the information that you need to do this.
03-29-2010 03:12 AM
03-29-2010 09:28 AM
Are these pins also on the ILA trigger port? and used as part of the trigger qualifier? If not then this is likely your problem.
The other potential issue is the ILA clock that is used to capture the data. The clock must be synchronous with the data. Since IIC runs very slow (400kbps max), the IIC core is likely gating the data input/output to slow it down from the faster internal clock. You will also need to take this into consideration.
03-30-2010 08:56 PM
I have added the I2C signals as trigger and chosen the M1/sys_clk_s net as the clock. sys_clk_s is only clock I can see inside MicroBlaze. In the technology schematic, I can see that the I2C wrapper is getting this as the clock signal. Still I cannot see any change in the I2C signals in ChipScope.
Also I have observed that both these signals are always Low. They do not get triggered if I chose R, F or 1 trigger condition.
03-31-2010 12:54 PM
What you are reporting, the I2C link/application is working, but the transitions are not being shown in the ChipScope ILA core, doesn't make sense.
Do you have other trigger qualifiers? Or are you just triggering on the SDA output signal?
I would suggest that you check the placed and routed design in FPGA Editor to verify that the right nets were connected.
04-02-2010 04:43 AM