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494 Views
Registered: ‎02-28-2019

Debug Hub Core not detected

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Hello,

I am trying to create an automated testing program for a DDR3 module. This means I need to set up an Integrated Logic Analyzer(ILA) IP-Core. I have used it once in the past and it worked pretty well. I tried to set up an ILA for this project in as similarly as possible, but when I run it I get a block of warnings that end with the debug hub core being dropped. I should also mention that the only big difference between this project and the last one I used an ILA in is that this project uses a differential clock while the other used a standard single-ended clock. To convert the differential signal into a standard clock I used the following code:

 

Clk <= clkP and not clkN;

 

Then I used clk as the clock signal for the program as well as the clock input of the ILA. Is this correct or could it be causing my issues?

Secondly, and most importantly, when I run the program I get the following block of messages:

 

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.

INFO: [Labtools 27-1434] Device xc7k160t (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.

WARNING: [Labtools 27-3361] The debug hub core was not detected.

Resolution:

  1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
  2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use ‘get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]’.

WARNING: [Labtools 27-3413] Dropping logic core with cellname: ‘u_ila_0’ at location ‘uuid_23E7D65A79B59F7BC47406C1714DFAE’ from probes file, since it cannot be found on the programmed device.

WARNING: [Labtools 27-3413] Dropping logic core with cellname: ‘debugger’ at location ‘uuid_BE58990ED9335A1BBE82DCB6093F493E’ from probes file, since it cannot be found on the programmed device.

This is the entire message block I get and I really don’t know why I am getting these errors. I have tried playing with the clock to no avail. Can anyone help?

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Moderator
Moderator
440 Views
Registered: ‎02-09-2017

Re: Debug Hub Core not detected

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Hi @michael.piron ,

 

I believe the issue is with the clock input.

That is not the way to convert a differential clock into a single-ended.

First, you need to be sure that the inout pins are Clock Capable / Global Clock pins (not all the FPGA pin are capable of / supposed to receive a clock input).

Second, you need to instantiate and IBUFDS primitive, which will do the conversion for you. Here's how you instantiate an IBUFDS in verilog for a US/US+ device:

IBUFDS #(
.DQS_BIAS("FALSE") // (FALSE, TRUE)
)
IBUFDS_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
.IB(IB) // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);
// End of IBUFDS_inst instantiation

More information on this primitive, as well as examples in VHDL are available in the document UltraScale Architecture Libraries Guide - UG974 or 7 Series Libraries Guide - UG953.

Finally, the output O of the IBUFDS is the clock you will use to connect to the rest of the logic.

Let us know if you have any questions.

Thanks,

Andre Guerrero

Product Applications Engineer

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Moderator
Moderator
441 Views
Registered: ‎02-09-2017

Re: Debug Hub Core not detected

Jump to solution

Hi @michael.piron ,

 

I believe the issue is with the clock input.

That is not the way to convert a differential clock into a single-ended.

First, you need to be sure that the inout pins are Clock Capable / Global Clock pins (not all the FPGA pin are capable of / supposed to receive a clock input).

Second, you need to instantiate and IBUFDS primitive, which will do the conversion for you. Here's how you instantiate an IBUFDS in verilog for a US/US+ device:

IBUFDS #(
.DQS_BIAS("FALSE") // (FALSE, TRUE)
)
IBUFDS_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
.IB(IB) // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);
// End of IBUFDS_inst instantiation

More information on this primitive, as well as examples in VHDL are available in the document UltraScale Architecture Libraries Guide - UG974 or 7 Series Libraries Guide - UG953.

Finally, the output O of the IBUFDS is the clock you will use to connect to the rest of the logic.

Let us know if you have any questions.

Thanks,

Andre Guerrero

Product Applications Engineer

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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