cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
brucekaraffa
Observer
Observer
8,041 Views
Registered: ‎06-06-2014

Default state of VIO output signals

If I instantiate a chipscope VIO core in an FPGA what are states of the output signals if there is no JTAG connection to the FPGA?  Are the outputs at logic 0 or logic 1?

Tags (1)
1 Reply
bcarltontrex
Participant
Participant
2,769 Views
Registered: ‎01-30-2017

@brucekaraffa This is set when you customize the IP. Under the PRO_OUT Ports(x..y) tab, there is an Initial Value (in hex).

 

These names from Vivado 2016.4.

0 Kudos