If I instantiate a chipscope VIO core in an FPGA what are states of the output signals if there is no JTAG connection to the FPGA? Are the outputs at logic 0 or logic 1?
@brucekaraffa This is set when you customize the IP. Under the PRO_OUT Ports(x..y) tab, there is an Initial Value (in hex).
These names from Vivado 2016.4.