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Zoro100
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Registered: ‎05-22-2018

Do constraints need to be defined for debugging after using system ILAs?

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Hi everyone,

 

I am using Vivado 2018.2 for my current project. I am relatively new to this environment and I am trying to mark certain connections as debug. the automation wizard pops up and inserts system ILAs once I do that. I have assigned the clock and adjusted the probe widths for the ILAs that are being used. However I am very new to using ILAs.

 

The question might sound weird but I would like to know if I have to still include constraints related to debug probes and nets when I have system ILAs to do the task.

Can someone suggest if what I implied makes sense? If not, can someone suggest how do I proceed?

 

Thanks in advance,

 

 

-Chandrasekhar DVS

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dpaul24
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Registered: ‎08-07-2014

@Zoro100 ,

The question might sound weird but I would like to know if I have to still include constraints related to debug probes and nets when I have system ILAs to do the task.

Can someone suggest if what I implied makes sense? If not, can someone suggest how do I proceed?

No, as an user you do not need to set constraints for ILAs, the cores come with their own constraints. Think of them like tap-outs inside the design and so do not affect your data. However they affect design placement and consequently routing of signals.

To know about the core read this - https://www.xilinx.com/support/documentation/ip_documentation/ila/v6_2/pg172-ila.pdf

To get an idea how to use read this - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug936-vivado-tutorial-programming-debugging.pdf

 

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dpaul24
Scholar
Scholar
727 Views
Registered: ‎08-07-2014

@Zoro100 ,

The question might sound weird but I would like to know if I have to still include constraints related to debug probes and nets when I have system ILAs to do the task.

Can someone suggest if what I implied makes sense? If not, can someone suggest how do I proceed?

No, as an user you do not need to set constraints for ILAs, the cores come with their own constraints. Think of them like tap-outs inside the design and so do not affect your data. However they affect design placement and consequently routing of signals.

To know about the core read this - https://www.xilinx.com/support/documentation/ip_documentation/ila/v6_2/pg172-ila.pdf

To get an idea how to use read this - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug936-vivado-tutorial-programming-debugging.pdf

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

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Zoro100
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Registered: ‎05-22-2018

Thanks for the clarification @dpaul24 !

Also there are 'system ILA' and 'ILA(Integrated Logic Analyzer)' IPs in the IP catalog. I saw in some videos that the configuration mechanism is same for both the IPs. Apart from that, are there any other notable differences between them?

 

-Chandrasekhar DVS

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