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Registered: ‎08-28-2019

Dropping debug core

I inserted some debug cores to capture the value of some wires. And I can see these debug cores in IMPLEMENTATION, but when I generated bitstream, the cores are dropped. How can I solve it? THANKS!

debug_core_dropping.JPG

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Moderator
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Registered: ‎02-09-2017

Re: Dropping debug core

Hi xzwang@hnu.edu.cn,

What kind of device are you using? Is it a pure FPGA or is it a Zynq device? And what is the family and model?

In addition, where does the clock for the ILA comes from? Where is it generated? Does it pass by any modification block such as MMCM/PLL?

Thanks,

Andre Guerrero

Product Applications Engineer

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