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Visitor poelslager
Visitor
3,188 Views
Registered: ‎06-30-2017

ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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I have added debug to my design using the'Set Up Debug', but after programming the FPGA I get the following error:

 

ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch
probe_1=uuid_23E7D65A79BC59F7BC47406C1714DFAE (design_1_i/PAS_DMA_0/U0/bytes_left_sig[31:0])
probe_2=1:0-0 (u_ila_0_address_out_sig[31:0])

 

After removing the probes reference by the error and re-spinning everything, I get the same error again, but referencing different probes:

 

ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch
probe_1=uuid_23E7D65A79BC59F7BC47406C1714DFAE (design_1_i/PAS_DMA_0/U0/chan_sel_sig[5:0])
probe_2=1:0-0 (design_1_i/PAS_DMA_0/U0/PAS_DMA_v1_0_M00_AXI_inst/chanstate[3:0])

 

I've also tried deleting the .xdc files to let the 'Set Up Debug' dialog start fresh, but this doesn't seem to help.

 

What is going on here, how do I troubleshoot this?

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Visitor poelslager
Visitor
3,937 Views
Registered: ‎06-30-2017

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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I was using mark_debug on all the signals that I wanted to probe.  That didn't work.

 

All I could do to make this work was to manually add outputs to the IP that I'm working on and push it to a system_ila block in the block diagram.

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Visitor poelslager
Visitor
3,176 Views
Registered: ‎06-30-2017

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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Update:

 

After removing the two probes in the second error, the the ILA seems to work after programming.  But when I re-add the signals that I actually need to probe, the error pops up again.  What could cause this?

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Visitor poelslager
Visitor
3,163 Views
Registered: ‎06-30-2017

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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More information:

 

The following TCL command doesn't work:

 

write_debug_probes -force probesfile.ltx

 

Output is:

ERROR: [Vivado 12-5829] Unable to generate LTX file since debug core UUIDs are unavailable for unimplemented cores. Resolution: Issue the write_debug_probes TCL command after opt_design (or implement_debug_core) step has been run
ERROR: [Common 17-39] 'write_debug_probes' failed due to earlier errors.

 

So I run:

implement_debug_core

write_debug_probes -force probesfile.ltx

 

After programming the FPGA with the latest probes file, the original error still occurs.

 

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Moderator
Moderator
3,156 Views
Registered: ‎10-19-2011

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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Are you flattening the hierarchy? Are you already using the mark_debug on the nets that you want to probe? If not that might help. Alternatively you could instantiate the core manually, instead of using the wizard flow, go through the IP catalog and manually add the core, then stitch up your probes. 

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Visitor poelslager
Visitor
3,938 Views
Registered: ‎06-30-2017

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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I was using mark_debug on all the signals that I wanted to probe.  That didn't work.

 

All I could do to make this work was to manually add outputs to the IP that I'm working on and push it to a system_ila block in the block diagram.

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Observer mennsesc
Observer
2,769 Views
Registered: ‎03-02-2012

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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I get this error more than a day.  The only way I can fix it is to quit then restart Vivado with the same project.  Restarting Vivado fixes the problem every time.

Scholar wzab
Scholar
1,866 Views
Registered: ‎08-24-2011

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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Thanks a lot. I was fighting with that for one hour, until I have found your simple solution - quit and restart Vivado.
It worked perfectly!
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Adventurer
Adventurer
1,434 Views
Registered: ‎12-10-2014

Re: ERROR: [Common 17-70] Application Exception: CORE_LOCATION mismatch

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I got the same error while trying to probe some internal signals. Yup, restarting Vivado fixes it.

This looks like a major Vivado bug. using version 2018.1

 

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