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Visitor
Visitor
12,742 Views
Registered: ‎05-20-2012

ERROR NGDBUILD 604 while building system in FPGA in the loop(FIL) wizard

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Hello everyone,

this forum has been of great help to me so far, but now I have encountered a problem I can't figure out, so I would like your help, if you don't mind.

 

I'm conducting my dissertation and this is it:

 

I've created a Base System on XPS 13.4 which includes a ppc440, a 128kB BRAM and an RS232 as basic peripherals. I've also added a core implementing a row by column multiplier. I generated the bistream and wrote a testscript on the SDK and I monitor the system's behaviour with the chipscope  ILA. So far, everything works the way I intended.

My goal is to input my system into Matlab Simulink via the system generator, in order to use it as a controller in a predictive control system.

Thus, I execute the "FPGA in the Loop" (FIL) Wizard in Matlab, I add the system.vhd as a top level file I try to build the system

 

This is the part of the output that contains the errors

 

Checking expanded design ...
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/core_0' with type 'core_0_wrapper'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'core_0_wrapper' is not
   supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/proc_sys_reset_0' with type
   'proc_sys_reset_0_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'proc_sys_reset_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/jtagppc_cntlr_inst' with type
   'jtagppc_cntlr_inst_wrapper' could not be resolved. A pin name misspelling
   can cause this, a missing edif or ngc file, case mismatch between the block
   name and the edif or ngc file name, or the misspelling of a type name. Symbol
   'jtagppc_cntlr_inst_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/clock_generator_0' with type
   'clock_generator_0_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'clock_generator_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/RS232_Uart_1' with type
   'rs232_uart_1_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'rs232_uart_1_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/xps_bram_if_cntlr_1_bram' with type
   'xps_bram_if_cntlr_1_bram_wrapper' could not be resolved. A pin name
   misspelling can cause this, a missing edif or ngc file, case mismatch between
   the block name and the edif or ngc file name, or the misspelling of a type
   name. Symbol 'xps_bram_if_cntlr_1_bram_wrapper' is not supported in target
   'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/xps_bram_if_cntlr_1' with type
   'xps_bram_if_cntlr_1_wrapper' could not be resolved. A pin name misspelling
   can cause this, a missing edif or ngc file, case mismatch between the block
   name and the edif or ngc file name, or the misspelling of a type name. Symbol
   'xps_bram_if_cntlr_1_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/plb_v46_0' with type
   'plb_v46_0_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'plb_v46_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block
   'u_FILCore_Inst/u_system_wrapper/u_system/ppc440_0' with type
   'ppc440_0_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'ppc440_0_wrapper' is not supported in target 'virtex5'.

 I've already encountered a thread that explains that the solution has to do with netlists and ngc files, however I can't figure out what to do.

 

Thank you in advance for your time, I'd be more than grateful for a reply

Nick

 

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Xilinx Employee
Xilinx Employee
15,697 Views
Registered: ‎08-02-2011

It looks like you need to include .ngc netlists for synthesized modules into your FIL process. Please see Mathworks documentation for this information (I am not familiar with how to do that for this particular tool).

 

In short, the tools are looking for netlists that are not specified. They are declared in your code (as black boxes) so they are expecting you to also provide a netlist that it can use to continue through the implementation flow. But since you only specified the top level HDL file, it doesn't know where to find definitions for those lower level modules.

www.xilinx.com

View solution in original post

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Highlighted
Xilinx Employee
Xilinx Employee
15,698 Views
Registered: ‎08-02-2011

It looks like you need to include .ngc netlists for synthesized modules into your FIL process. Please see Mathworks documentation for this information (I am not familiar with how to do that for this particular tool).

 

In short, the tools are looking for netlists that are not specified. They are declared in your code (as black boxes) so they are expecting you to also provide a netlist that it can use to continue through the implementation flow. But since you only specified the top level HDL file, it doesn't know where to find definitions for those lower level modules.

www.xilinx.com

View solution in original post

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Visitor
Visitor
12,634 Views
Registered: ‎05-20-2012

Yes!

I included the .ngc files and it works!

thank you very very much

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Visitor
Visitor
11,842 Views
Registered: ‎01-06-2013

Hi.,

Where i will get that .ngc file to include and where i have to include that file

Please clarify this....

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Visitor
Visitor
11,128 Views
Registered: ‎06-13-2013

Hi an_fpga,

Could you please tell me :

1. Where is this .ngc file ?

2. How to include?

Many thanks.

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Newbie
Newbie
6,228 Views
Registered: ‎05-28-2016

When HDL code is generated by System generator, it creates directory named "sysgen" which contains all the VHDL/Verilog files as well as wrapping files. Please select top level HDL file from this directory in order to make your design work. 

Thanks!!

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