07-11-2013 02:29 AM
Hi , when executing Bitgen , I got the following errors with ML605 , Xilinx EDK 13.1,
and I also using Chipscope with my custom IP .
ERROR:PhysDesignRules:2105 - Issue with pin connections and/or configuration on
block:<jaip_0/jaip_0/USER_LOGIC_I/MP/Prof_Table/Mram_CacheMEM11>:<RAMB18E1_RA
MB18E1>. For TDP mode, REGCLKB should be tied off to 0 when DOB_REG is 0.
ERROR:PhysDesignRules:2108 - Issue with pin connections and/or configuration on
block:<jaip_0/jaip_0/USER_LOGIC_I/MP/Prof_Table/Mram_CacheMEM21>:<RAMB18E1_RA
MB18E1>. For TDP or SDP mode, REGCLKARDRCLK should be tied off to 0 when
DOA_REG is 0.
ERROR:PhysDesignRules:2105 - Issue with pin connections and/or configuration on
block:<jaip_0/jaip_0/USER_LOGIC_I/MP/Prof_Table/Mram_CacheMEM21>:<RAMB18E1_RA
MB18E1>. For TDP mode, REGCLKB should be tied off to 0 when DOB_REG is 0.
and so many similar error like this.
But Bitgen works well on EDK 13.1 if using ML507 , with the same custom IP
so I think my design is ok
my MHS file is attached below
after reading AR 42000
http://www.xilinx.com/support/answers/42000.htm
I don't understand which XCO file should be modified
should I modified the XCO file under [EDK project folder] / implementation ??
Can someone explain that ?
Thanks
07-27-2013 11:27 PM