Encrypted IP cores - power analysis (RS encoder / decoder)
Dear Xilinx users,
I am using Reed-Solomon encoders and encoders and I would like to estimate power consumed by all my modules and all IPcores (whole FPGA, including RS IP cores). I have read in ug907 that:
"If your design contains any encrypted IP/Blocks, your simulator will not dump the SAIF information for those IP/Blocks and for any internal blocks within the encrypted hierarchy. This incomplete SAIF information might affect the power estimation accuracy."
Is this true also for post-synthesize and post-implementation activity simulations? As far I know my RS ipcores are encrypted. I have generated post-implementation netlist and I see in the file encrypted data. Thus, I presume that these are IP cores form Xilinx. Does it means that there is no way to get IP cores activity signals and perform accurate power analysis with a SAIF/VCD file? Did anyone solve the problem?
To perform functional post implementation and functional post synthesize simulation, should I just click "Run post-synthesize functional simulation" in Vivado, or I need to generate the netlist of the design and perform the simulation manually? If I click the Vivado function "post-synthesize functional simulation" then I have a feeling that it is just simple behavioural simulation of the VHDL code. Please see the attached print-screen.