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Visitor elikelik
Visitor
15,892 Views
Registered: ‎09-24-2013

Error when programming design which contains ILA

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Hi,

 

I generate a design with ILA in Vivado.

 

When there is no ILA, the design can be programmed and is functional.

When ILA is added, in some compilations the following error is issued by the programmer right after the device is programmed:


ERROR: [Labtools 27-1437] Failed to get a response from the Debug Core Hub on device
XC7K325T_0 (JTAG device index = 0), in user chain = 1.
Resolution:
1) Verify that the clock signal connected to the debug core is clean and free-running.
2) Verify that the clock connected to the debug core meets all timing constraints.

 

What can be the cause for this?

 

Please advise.

 

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Xilinx Employee
Xilinx Employee
25,483 Views
Registered: ‎09-20-2012

Re: Error when programming design which contains ILA

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Hi,

 

Are you using KC705 evaluation kit?

 

Are you connecting the clock pin of ILA to the oscillator pins correctly?

 

Check if this helps http://www.xilinx.com/support/answers/52939.html

 

Thanks,

Deepika.

Thanks,
Deepika.
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8 Replies
Xilinx Employee
Xilinx Employee
25,484 Views
Registered: ‎09-20-2012

Re: Error when programming design which contains ILA

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Hi,

 

Are you using KC705 evaluation kit?

 

Are you connecting the clock pin of ILA to the oscillator pins correctly?

 

Check if this helps http://www.xilinx.com/support/answers/52939.html

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Visitor elikelik
Visitor
15,877 Views
Registered: ‎09-24-2013

Re: Error when programming design which contains ILA

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Thank you very much for your help,

 

indeed a clock was missing during programming.

The reason that some ILAs worked is that I was working with 2 ILAs - each for a different clock domain.

When the Debug Core hub was fed with the missing clock, I got the error.

When the Debug Core hub was fed with the second clock (which was operating during programming) - everything was OK.

 

 

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Visitor sebwerner
Visitor
14,603 Views
Registered: ‎07-21-2014

Re: Error when programming design which contains ILA

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Hi,

 

I get exactly the same Error message when i try to program the VC709 board. The clock i feed the ILA with is not an input port clock, it's a clock that is being generated in a module (PCS/PMA IP core) and passed to all other modules, including my ILA.

 

Does the clock the ILA is fed with have to be an input port clock to the chip? Because i correctly connect the generated clock to the ILA / hub cores.

 

Best wishes,

Sebastian

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Xilinx Employee
Xilinx Employee
14,589 Views
Registered: ‎03-24-2010

Re: Error when programming design which contains ILA

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If ILA clock will be stable some time after programming, refresh device after the clock become stable. Then the ILA will be detected.

Regards,
brucey
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Visitor sebwerner
Visitor
14,560 Views
Registered: ‎07-21-2014

Re: Error when programming design which contains ILA

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Thank you for your answer!


I did refresh several times, but i keep getting the same error

ERROR: [Labtools 27-147] vcse_server: XSDB Master timed out.
ERROR: [Labtools 27-1437] Failed to get a response from the Debug Core Hub on device xc7vx690t_0 (JTAG device index = 0), in user chain = 1.

 

I checked several times and the dbg_hub/clk net is connected, its type is 'global_clock' , route status is 'routed', even the Aliases show that its connected to the same clock as all other modules. I don't get this error if i program my desing on the FPGA without the ILA core. I create the clock with the create_clock command properly and everything seems fine despite this error. 

 

What else could be the issue here? 

 

Thanks a lot for your help, i'm really stuck here.

 

Best wishes,

 

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Xilinx Employee
Xilinx Employee
14,551 Views
Registered: ‎09-14-2007

Re: Error when programming design which contains ILA

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Hi,

 

Can you confirm that the debug hub clock is connected to a free running clock?

 

In order for the scan to work, it needs to be a connected to a free running clock and that clock needs to be always available.

 

Thanks

Duth

 

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Visitor sebwerner
Visitor
14,544 Views
Registered: ‎07-21-2014

Re: Error when programming design which contains ILA

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Hi,

 

thanks for your reply. Before i make a definite answer, in this context, what exactly do you consider as a 'free running clock' ? My design has a differential input clock pair refclk_p and refclk_n, which the PCS/PMA IP core uses to generate the 156.25Mhz clock that all my modules use, including the ILA/dbg_hub.

 

I tried to connect the refclk_p input port clock to the dbg_hub, but that wasn't possible as this is of type 'signal'.

 

Best wishes

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Visitor sebwerner
Visitor
14,535 Views
Registered: ‎07-21-2014

Re: Error when programming design which contains ILA

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my constraint file says:

 

create_clock -period 6.400 -name clk156 [get_ports refclk_p]

set_property IOSTANDARD LVDS [get_ports refclk_p]
set_property IOSTANDARD LVDS [get_ports refclk_n]
set_property PACKAGE_PIN AH7 [get_ports refclk_n]
set_property PACKAGE_PIN AH8 [get_ports refclk_p]

 

I'm working on the VC709 Evaluation Board.

Hope that helps.

 

Best wishes

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