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Anonymous
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FPGA Debug using ILA - Painful or Painless?

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Hello, I've watched a view videos on the ILA tool and it seems like a lot of work when comparing to Quartus Signal Tap. Why is that, or am I missing something? Is there tool in Vivado that one can quickly get going without having to insert debug lines into your HDL code? 

 

Thanks,

Joe

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Registered: ‎02-09-2017

Re: FPGA Debug using ILA - Painful or Painless?

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Hi @Anonymous,

 

Yes, there is an easier way to insert the ILA that does not involves writing HDL code.

It's called ILA Insertion Flow and it's done after you've finished the Synthesis, by clicking on the Set Up Debug Wizard.

Set_up_debug_menu.JPG

The document Vivado Programming and Debugging - UG908, pg. 115, has a deeper explanation and example on how to use the Insertion Flow and Set Up Debug Wizard.

With this method, the only potential code that you might right is the mark_debug attribute, to tell Vivado that you will want to scope those nets later and prevent optimization. It would require you to add the statement before the signal/wire/bus declaration:

 

(* mark_debug = "true" *) wire [7:0] char_fifo_dout;

This is not mandatory. If you don't want to do it (or forgot to mark some signal), once the synthesis is complete, you can just open the synthesized schematic, find the net you need to analyze, right-click on it and select "Mark Debug". Or you can also run a XDC command, such as:

set_property mark_debug true [get_nets my_net]

Please let me know if you have any questions.

Thank you,

Andre Guerrero

Product Applications Engineer

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Moderator
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502 Views
Registered: ‎02-09-2017

Re: FPGA Debug using ILA - Painful or Painless?

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Hi @Anonymous,

 

Yes, there is an easier way to insert the ILA that does not involves writing HDL code.

It's called ILA Insertion Flow and it's done after you've finished the Synthesis, by clicking on the Set Up Debug Wizard.

Set_up_debug_menu.JPG

The document Vivado Programming and Debugging - UG908, pg. 115, has a deeper explanation and example on how to use the Insertion Flow and Set Up Debug Wizard.

With this method, the only potential code that you might right is the mark_debug attribute, to tell Vivado that you will want to scope those nets later and prevent optimization. It would require you to add the statement before the signal/wire/bus declaration:

 

(* mark_debug = "true" *) wire [7:0] char_fifo_dout;

This is not mandatory. If you don't want to do it (or forgot to mark some signal), once the synthesis is complete, you can just open the synthesized schematic, find the net you need to analyze, right-click on it and select "Mark Debug". Or you can also run a XDC command, such as:

set_property mark_debug true [get_nets my_net]

Please let me know if you have any questions.

Thank you,

Andre Guerrero

Product Applications Engineer

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-------------------------------------------------------------------------

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