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scottmrrll
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Registered: ‎07-29-2019

FPGA utilization

Please give an opinion of the utilization of this device from the attached report.  My confusion is that the Slice Register and LUT as Logic utilization is so low yet the over all slice is 78.58%.  Its my understanding that each slice has 2 outputs, on registered and the is not, so:

1) If we continue adding logic will it try to use some of the already used 6404 slices and the possibly un-used outputs that might exist?

2) We figure we are about 90% complete with the design.  If our design goal is to stay under 80% utilization when introducing the product, in your opinion should we be changing the FPGA now for a bigger device?

Thanks in Advance,

Scott

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dpaul24
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Registered: ‎08-07-2014

@scottmrrll ,

2) We figure we are about 90% complete with the design. If our design goal is to stay under 80% utilization when introducing the product, in your opinion should we be changing the FPGA now for a bigger device?

My experience with Artix7 FPGA is that if the logic utilization is over 90% then Vivado finds it very difficult to route the design. Even if at the end Vivado does manage to place and then route, the total run time required for the Impl stage significantly increases.

I would suggest for Xilinx 7 series FPGAs, keep device utilization to a max of 80-85%. If one can sense that the logic utilization is more in early design stage, my recommendation is to go for a bigger FPGA.

I cannot comment about US or US+ devices.

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scottmrrll
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Registered: ‎07-29-2019

Thanks, sounds like good advice.

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joancab
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Registered: ‎05-11-2015

I would say the rule is the same for any FPGA family. Is quite a delicate choice. Difficult to draw a line at X%. I will just drop the pros and cons for every option:

a. go for a bigger device if utilization reaches 75-80-85%

Pros: Leaves space for improvement and post-production add-ons

         Better routing and timing closure. I would prefer this if a high speed or tough to time closure

Cons: obviously, higher cost. A risk to consider for a low-cost product

b. Stay and squeeze

Pros: Low cost

Cons: Upgrades and even changes may be impossible

          As it fills up, timing may need to be relaxed (==> lower speed)

scottmrrll
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Registered: ‎07-29-2019

Okay thanks.

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scottmrrll
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Registered: ‎07-29-2019

What is most important to look for utilization?  Vivado gives didn't numbers for Slice 78.58%, then LUT as Logic 50.6% ,and finally Slice registers 27%.  To gauge absolute utilization what should be most considered?

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joancab
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Registered: ‎05-11-2015

Everything. When you run out of something, it's done. When you are close to, resources may not be located in the best locations, so performance may drop.

Some designs have a large usage of some type of elements, to me that's the limiting factor, so it depends on the design. It could be BRAM, or LUTs, or MMCMs.

I have done the following to check how full a chip is: implement your design, get the timing report, etc. Then add an independent dummy piece of HDL that uses some additional 10%, ideally using all types of elements, re-implement and compare, especially timing. At least I look more professional than just saying "I think it will be fine".

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dpaul24
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Registered: ‎08-07-2014

@scottmrrll ,

In general everything.

But I would still put it this way....

If you know that your next design changes is all of logic then consider the LUT utilization. If your next changes will utilize a lot of memory and few logic, then focus should be put on BRAM utilization and so on....

e.g. - In a scenario where your design has current BRAM util of 85% and the changes you want to make will consume two more 36K BRAM blocks and some logic elements (LUT, lets say current LUT util is at 80%) then you can still go ahead with the change on the same FPGA chip.

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