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Observer emil_kruki
Observer
8,829 Views
Registered: ‎11-26-2011

Fail-Safe Design in Spartan-6 Family with ISE 13.4

Hi everybody,

I've been trying to run Fail-Safe Design in Spartan-6 Family tutorial on ISE 13.4. Everything was done without any problems.

Isolation verification tool doesn't notify any violations, when I run the chek against UCF. But by running a check against the netlist, I became so much violations related to Tile summary. Hier is the extract of the report:

 

  Tile Adjacency

    Net Adjacency Violations: 60
    Logic Adjacency Violations: 0

  Tile Content

    Net Content Violations: 7
    Logic Content Violations: 15

  Inter-region Signals

    Inter-region Net PIP Violations: 79
    Inter-region Load Violations: 0

 

I attach also SVG files of UCF and netlist check.

 

Do you have any idea, what can be wrong in my design?

 

Best regards,

Emil Gracic

SCC_LAB_TOP_ucf.svg
SCC_LAB_TOP_ucf.svg
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2 Replies
Scholar austin
Scholar
8,815 Views
Registered: ‎02-27-2008

Re: Fail-Safe Design in Spartan-6 Family with ISE 13.4

Check that your regions have the proper spacing (distance) for each other,

 

There must be unused logic and routing sufficiently wide between regions so there is no possibility of a defect or failure creating a connection.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer emil_kruki
Observer
8,803 Views
Registered: ‎11-26-2011

Re: Fail-Safe Design in Spartan-6 Family with ISE 13.4

Thanks for reply,

as said, I followed the instructions from tutorial, and everything was done identical as in tutorial. Only the version of Xilinx ISE is not the same: In tutorial will be used 12.4 and I've been using 13.4...

 

Best regards,

Emil Gracic

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