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Observer 123mutt123
Observer
1,018 Views
Registered: ‎10-08-2018

Failure to connect to Dbg_hub on zc706 BIST project

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I am find find that the debug hub inserted into my design is not detected on the Jtag Chain connected via the diligent cable.

My design has been verified on a ZC702 Dev board and I have migrated the design onto the ZC706 board, and to 2018_2 toolset. The data channel does not transmit data on that board and I am therefore attempting to identify where the data is stopping.

I have followed the process in UG908 for Post Synthesis net selection with MARK_DEBUG and Setup Debug. The selected clock is that which clocks the data through the PL and originates on a Lime Software Defined Radio board with an attached Signal Generator as Clock Reference. The clok rate is 51000000. Otherwise defaults are selected in the Setup Debug Wizard. All expected ILA and DBG_HUB cores are present in schematics and appear in the Implemented design.

When the board is flashed, the following warning appears.

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.

Anticipating a need to share the project settings I have migrated the ZC706 BIST project to 2018_2 and Marked several DDR and AXI nets for debug following the same steps. Attaching the HW_SERVER to ZC706 xc7Z045_1 at the lowest Jtag speed and programming yields the identical warning.


I have attempted this process multiple times, connecting the hw-manager at various Jtag frequencies all of which meet the 2.5xSlower requirement and the debug_hub is never detected.

get_property C_USER_SCAN_CHAIN returns 1

The BSCAN_SWITCH_USER_MASK is 0001 which I assume signifies that only scan chain 1 is passed. (I have also tried 1111 to allow all chains to pass)

Probe file is as follows

<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="2">
  <probeset name="EDA_PROBESET" active="true">
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="CORE_UUID" value="23e7d65a79bc59f7bc47406c1714dfae"/>
        <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="50000000"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="0"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="32"/>
      </probeOptions>
      <nets>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[31]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[30]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[29]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[28]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[27]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[26]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[25]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[24]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[23]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[22]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[21]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[20]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[19]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[18]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[17]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[16]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[15]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[14]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[13]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[12]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[11]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[10]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[9]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[8]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[7]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[6]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[5]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[4]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[3]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[2]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[1]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_portb_DOUT[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="CORE_UUID" value="23e7d65a79bc59f7bc47406c1714dfae"/>
        <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="50000000"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="1"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="4"/>
      </probeOptions>
      <nets>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARCACHE[3]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARCACHE[2]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARCACHE[1]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARCACHE[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="CORE_UUID" value="23e7d65a79bc59f7bc47406c1714dfae"/>
        <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="50000000"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="2"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="2"/>
      </probeOptions>
      <nets>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARBURST[1]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARBURST[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="CORE_UUID" value="23e7d65a79bc59f7bc47406c1714dfae"/>
        <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="50000000"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="3"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="12"/>
      </probeOptions>
      <nets>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[11]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[10]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[9]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[8]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[7]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[6]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[5]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[4]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[3]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[2]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[1]"/>
        <net name="system_i/processing_system7_0_axi_periph_m03_axi_ARADDR[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="CORE_UUID" value="23e7d65a79bc59f7bc47406c1714dfae"/>
        <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="50000000"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="4"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="32"/>
      </probeOptions>
      <nets>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[31]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[30]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[29]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[28]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[27]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[26]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[25]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[24]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[23]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[22]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[21]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[20]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[19]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[18]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[17]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[16]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[15]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[14]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[13]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[12]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[11]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[10]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[9]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[8]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[7]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[6]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[5]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[4]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[3]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[2]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[1]"/>
        <net name="system_i/axi_bram_ctrl_0_bram_porta_DOUT[0]"/>
      </nets>
    </probe>
  </probeset>
</probeData>

and hardware device properties are as follows


HardwareDeviceProperties.jpgxc7z045_1 hardware Device Props


Can anyone suggest what I am doing wrong? 


Many thanks

Matt.

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1 Solution

Accepted Solutions
Observer 123mutt123
Observer
900 Views
Registered: ‎10-08-2018

Re: Failure to connect to Dbg_hub on zc706 BIST project

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Andre,

 

thank you for your very reasonable suggestions.

 

I have done as you suggested. Firstly I attached LEDs to the Clock line and, having discovered that hte off board clock source needs to be programmed by Zync Software to forward the clock, I have proven that hte clock source is stable, free runing and all that.

My ila core and debug hub and data procesing chain are all clocked of that clk source pin and yet the debug hub does not appear in the Hardware Manager and so no probes appear.

Our situation is slightly complex, in that I need to start the PL and software from the SDK, but I am sure that the correct PL is being flashed. Should I expect to see the debug probes in Vivado HW manager under that startup regime?

I have also cut down the amount of debug requested. Now only a single net is being probed for a single bit.

 

Are you able to render any further assistance?

 

many thanks

Matt Burrows

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3 Replies
Moderator
Moderator
948 Views
Registered: ‎02-09-2017

Re: Failure to connect to Dbg_hub on zc706 BIST project

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Hi @123mutt123,

 

Since you mentioned that in the new board the data channel does not transmit data, I suspect there's some issue with the clock going into that board. The error you are seeing with the ILA in most cases is related to a clock not found as well.

How is that clock connected to the board? Is it passing through a MMCM/PLL? 

Could you modify your design to route that clock to an output LED to make sure it's working fine?

I'd also recommend that you simplify the ILA design and create an ILA with only one probe on it. That's the simplest it can get and help us eliminate any other issues with the ILA.

Thanks,

Andre Guerrero

Product Applications Engineer

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Observer 123mutt123
Observer
901 Views
Registered: ‎10-08-2018

Re: Failure to connect to Dbg_hub on zc706 BIST project

Jump to solution

Andre,

 

thank you for your very reasonable suggestions.

 

I have done as you suggested. Firstly I attached LEDs to the Clock line and, having discovered that hte off board clock source needs to be programmed by Zync Software to forward the clock, I have proven that hte clock source is stable, free runing and all that.

My ila core and debug hub and data procesing chain are all clocked of that clk source pin and yet the debug hub does not appear in the Hardware Manager and so no probes appear.

Our situation is slightly complex, in that I need to start the PL and software from the SDK, but I am sure that the correct PL is being flashed. Should I expect to see the debug probes in Vivado HW manager under that startup regime?

I have also cut down the amount of debug requested. Now only a single net is being probed for a single bit.

 

Are you able to render any further assistance?

 

many thanks

Matt Burrows

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Observer 123mutt123
Observer
893 Views
Registered: ‎10-08-2018

Re: Failure to connect to Dbg_hub on zc706 BIST project

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I have a solution now. It seems that the debug hub and ila only communicate if the PL is programmed from Vivado. I can then start the SW from the SDK and the debug hub appears in vivado hw manager (on refresh).

I also changed the Capture control in setup debug which may have helped.

thanks again

Matt

 

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