Frequency setting with XPA

[martur]

Hi,

i'm using xpa to estimate the dynamic power of my design.. when doing the simulation, xpa computes acceptable static and dynamic power values. The problem is, when i want to estimate these values using the only ncd file (place and route report of my design), the dynamic power is equal to zero..This seems to be obvious since the frequency taken as input is equal to zero. Actually, i want to ask, how the XPA calculates the input frequency? and why it is equal to zero? and my final question is: can i set manually the frequency in the input so that the dynamic power will be more realistic?

Thank you in advance

[gszakacs]

XPA does not try to calculate the frequency.  You must enter it manually if you don't

provide simulation data.  You can manually enter the clock frequencies in the

tables under Details --> By Clock Domain.  You might also want to change the

default activity rates under Project Settings.

[martur]

I tested Xilinx's example « S6_tutorial_top_16bit » without simulation data.I have just used ncd file. I didn't fix manually clk values and XPA estimates power correctly. In power report, I found that the input frequency were fixed at :
                                                      
|  Logic:                                                                      
|   pll_in_bufg_inst   = 33.00 MHz                                            
|  Nets:                                                                 
|   clk33_pll             = 32.87 MHz 
|   pll_in                   = 33.00 MHz 
|   CLK33_IBUF    = 33.00 MHz     
|   pll_clkfb             = 32.87 MHz      
|  Logic:                                                                  
|   SP6_BUFIO_INSERT_ML_BUFIO2_0      = 200.00 MHz 
|   SP6_INS_BUFIO2FB_DCM_ML_BUFIO2FB_1 = 199.87 MHz   
|   dcm_feedback_bufg_inst    = 199.87 MHz   
|   dcm_clk_bufg_inst              = 159.90 MHz 
|  Nets:                            
|   clk                                        = 159.90 MHz 
|   dcm_fbout                           = 199.87 MHz 
|   dcm_clk                               = 159.90 MHz 
|   DCM_SP_inst_ML_NEW_DIVCLK    = 200.00 MHz   
|   DCM_SP_inst_ML_NEW_O                =  199.87 MHz 
|   dcm_fbin                           = 199.87 MHz 
|   clk_ibufgds                       =  200.00 MHz 
 
so, my questions are :
In this example, how these clk's values were fixed ?? From where XPA extracted these values ?

thank you in advance

[gszakacs]

It's possible that the values came from constraints.  It's not clear how the constraints ended

up in the ncd file.  Perhaps it depends on how the constraints were defined (ucf vs HDL source, etc.).

[martur]

i just have a question about combinational circuits: how to calculate the dynamic power for circuit which doesn't contain a clock with the XPA tool? 

[gszakacs]

First I'd like to give a better answer to your previous question:

Loading a design I got the following warning:

WARNING:Power:1369 - Clock frequency for one or more clocks was not found through
timing constraints (PCF file) or simulation data.

This indicates that it is the physical constraints and not the user constraints used to

determine clock frequency.  In my case it was warning me about DQS signals which

MIG uses as clocks, but don't have a period constraint.  If for some reason your

period constraints did not propagate to the PCF file, then you could get this warning

when you start XPA.

---

@martur wrote:

i just have a question about combinational circuits: how to calculate the dynamic power for circuit which doesn't contain a clock with the XPA tool? 

---

If you look under Details --> By resource type --> IOs

You will get a table of all your inputs and outputs.  You can edit the signal rate and duty cycle (% high)

for each pin to estimate the actual dynamic power.  Of course it would be more accurate to provide

simulation data, instead.