04-05-2018 01:31 AM
Hi Friends,
I have design having ILA with some design nets and it was working functionally. then i add 4 nets(Those are ports) to ILA . Now after adding i did not get any timing violations but functionally some cases are not working. i removed some of previously nets from ILA , even though same funtional issue is comming.
I am comparing both post-route dcp's for routing . i did not get much from that. Can anyone help on this , what can be the issue.
any help or suggestions are highly appreciated.
Thank you
S Sampath
04-12-2018 02:41 AM
Actually the exatra added nets are from top level ports. i forgot to give pin location to one of the 4 signals, So it was choosing random pin{i tried 2 or 3 builds}. That is causing functional issue.
after constraining that it is fine. but i dont know why functional issue when i have not constraint pin locs.
Thank you
S Sampath
04-05-2018 01:45 AM
Hi @ssampath
Did you check the behavioral, post synthesis and post implementation functional simulation? Do all show same functionality mismatch once you add more nets to ILA?
Regards
Rohit
04-05-2018 01:48 AM
Consider ILA as a flexible software oscilloscope. ILA connections are merely be like wire tap-out points.
It shouldn't affect the functionality of a design (although inserting it affects timing, but this is not your case).
i removed some of previously nets from ILA , even though same funtional issue is comming.
Then I suspect that there is a problem in your design. It might be that previously it was working by chance!
Pay more attention to functional verification so as to find the issue. With the little info you have provided this is my best answer.
------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
04-05-2018 01:50 AM
04-05-2018 01:52 AM
04-12-2018 02:41 AM
Actually the exatra added nets are from top level ports. i forgot to give pin location to one of the 4 signals, So it was choosing random pin{i tried 2 or 3 builds}. That is causing functional issue.
after constraining that it is fine. but i dont know why functional issue when i have not constraint pin locs.
Thank you
S Sampath