Hardware Co-simulation - System generator

[zikou]

I work to implement a FIR filter in Virtex6 carte (ML605).

After VHDL coding  and simulation, I try to validate my design using Hardware Co-simulation with Xilinx system generator.

But, I have this error : "Error:Failed to implement the design as it could not meet 1 constraint. Try to optimize the critical paths or lower the clock frequency of the design. Please refer to 'xflow.results' for further details."

Really, I didn't need a high frequency and 10 MHz is enought for me.

I used the lowest frequency permit in settling 33 MHz, but always the same error.

Thanks in advance ,

Zied Koubaa

[mtechvlsi]

Sir,

I am facing the same problem during hardware co-simulation. Have you got any solution for this problem? If any, please reply.

Thanks in advance.

Shanoli

[zikou]

Until now, Ididn't found a solution for this error.