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Observer lhbhp
Observer
8,517 Views
Registered: ‎01-16-2015

How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

Hi guys,

 I package an IP, which has some I/O signals. They should be tri-state inout type.

 In the IP design I set it as "I","O" and "T".When I do this in ISE, I can modify the *.mpd to make it be one I/O pin. So how can I do this in VIVADO 2015.2 ?

 Can you help me ?

 

Thanks a lot,

Lew

IOT.png
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7 Replies
Scholar trenz-al
Scholar
8,508 Views
Registered: ‎11-09-2013

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

set GPIO bus assign _O _T _I then it looks like 1 wire in IPI BD and vivado builds the io buffer for you

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Observer lhbhp
Observer
8,468 Views
Registered: ‎01-16-2015

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

Hi @trenz-al,

 So you mean I should do "set GPIO bus assign _O _T _I " in verilog code or in I/O planning ?

 

Thanks a lot,

Lew

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Observer lhbhp
Observer
8,465 Views
Registered: ‎01-16-2015

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

Hi @trenz-al,

 I find AXI GPIO IP core, should I use this? But can I use inout without AXI bus ?

 

Thanks,

Lew

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Xilinx Employee
Xilinx Employee
8,441 Views
Registered: ‎07-21-2014

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

Hi,
regarding your first query,
You can use interface definition editor
Because a device does not have true tristate lines inside the fabric, a triple of signals (in, out, tristate) represents a tristate pair (in, out, tristate).
You can refer to following UG1118 page#78

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug1118-vivado-creating-packaging-custom-ip.pdf

-Shreyas
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Observer lhbhp
Observer
8,410 Views
Registered: ‎01-16-2015

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

Hi @aher,

 Thanks for your suggestion. I will try it.

 

Thanks,

Lew

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Observer lhbhp
Observer
8,407 Views
Registered: ‎01-16-2015

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

Hi @aher,

 I just see some description , but I really don't know how to put these three signals in a tristate...

 

Thanks,

Lew

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Scholar trenz-al
Scholar
8,272 Views
Registered: ‎11-09-2013

Re: How can I set tri-state for signals when I package an IP in VIVADO 2015.2?

you use GPIO interface

 

when ever _T is HIGH the generated IO pin is in tristate

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