10-08-2020 03:14 PM
We are troubleshooting a customer device now. I can re-create the build and load it, and I see the same problem that was reported. But if I insert ILAs into the design (which is done post-synthesis), the problem goes away. Is there a way to probe or debug that keeps the layout the same?
I can re-build the original design, then load it onto the part via JTAG (rather than using the external flash). We see the same problem. However, if I insert ILAs (post-synthesis) and download the new image, the problem goes away. There are no issues when a new layout with ILAs is loaded. It is only the original, unaltered image that seems to fail.
Is there a way to look inside the FPGA without going through a new place and route? Perhaps add ILAs or something like it to observe signals in the current layout? If not, is there a JTAG means to scan for damage to the internal logic?
10-08-2020 04:35 PM
But if I insert ILAs into the design (which is done post-synthesis), the problem goes away.
This sounds like a timing problem, which is something you are unlikely to find with probes of any kind.
Timing problems are usually solved by careful review of timing constraints and clock-crossings used in your design.
Please describe the symptoms of the problem in detail and any other troubleshooting you have done to isolate the problem. Does the problem appear on more than one board?
10-11-2020 09:59 PM - edited 10-11-2020 10:00 PM
Kindly run following TCL commands after opening your implemented design (in both working and non-working) and check for design timing issues
For more detailed understanding of above commands please check https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug906-vivado-design-analysis.pdf