How to check glitch on clock net?

[haipham]

Hi everyone.
I face with a glitch error on my clock net. Are there any body have experience to check the glitch like this.
I am using Kintex KC705 and Vivado 14.03.
Thanks

[thakurr]

Hi @haipham

What is the complete clock net path?

[haipham]

Here you are.
The clock structure as below.

[haipham]

I continue to probe all path clk_in_b <- clk_in_a <- clk_in <- CLK_100MHZ_TOP <- CKIN_P if getting glitch or not.
What solution should I apply if CKIN_P is not stable?

[thakurr]

Hi @haipham

It is generally recommended that if you wish to divide a clock, you should use clock management component such as MMCM, PLL. Failing to do so, result in clock using local routing network using LUTs, F/Fs and It is very difficult to ensure that the clock gated in a LUT is glitch free.

Here is the helpful link for you:

https://forums.xilinx.com/t5/General-Technical-Discussion/Reg-Clock-gating-for-FPGAs-good-or-bad/td-p/279154

[haipham]

Hi @thakurrI has read your link. But my divider circuit is need in my asic application.
Just only use MMCM, PLL in FPGA wrapper.