08-09-2018 11:01 PM
I face with a glitch error on my clock net. Are there any body have experience to check the glitch like this.
I am using Kintex KC705 and Vivado 14.03.
08-09-2018 11:41 PM
What is the complete clock net path?
08-10-2018 03:19 AM
I continue to probe all path clk_in_b <- clk_in_a <- clk_in <- CLK_100MHZ_TOP <- CKIN_P if getting glitch or not.
What solution should I apply if CKIN_P is not stable?
08-10-2018 04:01 AM - edited 08-10-2018 05:09 AM
It is generally recommended that if you wish to divide a clock, you should use clock management component such as MMCM, PLL. Failing to do so, result in clock using local routing network using LUTs, F/Fs and It is very difficult to ensure that the clock gated in a LUT is glitch free.
Here is the helpful link for you: