08-07-2018 05:20 AM
Hello! I'm new to Vivado, so excuse me if the question is a little basic.
I need to create separate .dcp files, each to represent a module in my project. I assume it should reduce compilation/implementation time, as these modules won't be recompiled every time. I've figured out how to create .dcp (tcl command to set module out-of-context and synthesize, or set them temporary on top level and synthesize) and add dcp sources to project (with disabling corresponding .vhd-source files). But when it comes to implementation step, I'm starting to get constraint errors, like this:
[Chipscope 16-213] The debug port 'u_ila_0/probe0' has 1 unconnected channels (bits). This will cause errors during implementation.
The fact is that, everything worked fine, up to generating bitstream (with no dcp).
So, what changes do I have to make in project in order to be able to compile with .dcp? I'm using Vivado 2017.4, device is KINTEX 7 (xc7k160t ffg676-2).
08-20-2018 01:11 PM
That warning is saying that one of the bits from your ILA is unconnected. Please check how you have instantiated the ILA and connected its probe ports to the net in your design.
In addition, I've seen people using the ILA IP in the form you are using (DCPs) but it's not officially accepted or tested. It would be recommended that you just instantiate it in RTL, or use the Setup Debug Wizard after synthesis.
The approved ways of inserting an ILA in a design are described and exemplified in the document Vivado Programming and Debugging - UG908, Chapter 10.
08-22-2018 08:48 AM - edited 08-22-2018 08:49 AM
Thanks, I solved that issue by deleting all "attribute mark_debug of my_sign : signal is "TRUE"" lines from my module. But after that the next problem has emerged: how to output signal values to inspect them on diagrams, when I work with hardware using .dcp file?