06-11-2014 11:23 PM
i have done my deisgn in virtex-6, generated bit file and i am getting output . but i want to know how many gates is there in my design.
can you please tell me how to see number of gates that is Key feature for my design . because its an existing block i developed with new techniques so want to Prove my design has less gates compared to old design.
so any body can help me??/
06-11-2014 11:30 PM
06-11-2014 11:40 PM
can you please elabarate how can use report??
where i have to see in report???
06-11-2014 11:40 PM
If you want to compare FPGA basic elements, then comparing post PAR utilization which will be available in PAR report file will give you a good insight.
In addition, There was a good old xapp on how to relate gates to FPGA resources.
Hope this helps.
06-11-2014 11:51 PM - edited 06-11-2014 11:52 PM
You can find the information under Device Utilization summary in the .par file. This is automatically generated when you implement the design.
Attahing a screenshot for your reference.
06-12-2014 01:57 AM
thanks for ur reply. but here we will come to know how many LUT and how many registers but i want to know in terms of gates????
06-12-2014 02:07 AM
Yes thats right. We dont have the number in gates as its dependent on architecture and also in logical implementation.
Thats why in earlier post, I mentioned abt the white paper that kid of gives some information.
06-12-2014 02:18 AM
this document is good. with this i can understand approximate gate count. but i am using virtex-6,can you please share it for virtex-6 fa,mily type???
06-12-2014 02:47 AM
since I'm no Xilinx emplyee I can tell you the painful truth: FORGET IT!
You can find many long threads here and in comp.arch.fpga when you are searching for "gate equivalent" or "gate count".
To save your time, here's the short conclusion:
FPGAS are no ASICS. They just do not have gates.
So every attempt to do some gate equivalency estimation is just nonsense.
In the early days of FPGAs this was done sometimes for marketing purposes and to get ASIC designers in touch with FPGAs.
But then the devices just were plain LUTs and FFs.
Now you have BRAMs, DSP-Blocks and other Hardmacros (up to complete CPUs) in FPGAs and the LUTs have grown too.
Here's what to do if you want to compare two design alternatives:
Feed them both to an ASIC synthesis tool and also to a FPGA synthesi tool.
Compare the results for ASICs and FPGAs .
It might happen that design A performs better in ASICs while design B performs better in FPGAs.
You see, the gate count would be even misleading when you would apply the ASIC gate count to some FPGA implementation.
Have a nice synthesis
06-12-2014 05:54 AM
Unfortunately thats the only document. We dont have any for latest families.
06-12-2014 06:45 PM
I'm personally inclined to agree with Eilert here.
There are many of these threads (even here) but the short story is oranges != apples