How to make right .bmm file ?

shangdawei@gmail.com · ‎01-05-2010

i want to update BRAM without re-implement. to use data2mem, i need make .bmm file

at first i make .bmm to use Command: data2mem -mf p MYPPC PPC405 0 a ROM b 0x00000000 32 s RAMB16 0x8000 2 bank -o p auto.bmm

then i imp. without -bm and use xdl command line ( planahead, fpga editor etc.) to find instance of BRAM.

and modify auto.bmm :

///////////////////////////////////////////////////////////////////////////////
//
// Processor 'MYPPC', ID 0, memory map.
//
///////////////////////////////////////////////////////////////////////////////

ADDRESS_MAP MYPPC PPC405 0

    ///////////////////////////////////////////////////////////////////////////////
    //
    // Processor 'MYPPC' address space 'ROM' 0x00000000:0x00007FFF (32 KBytes).
    //
    ///////////////////////////////////////////////////////////////////////////////

    ADDRESS_SPACE ROM RAMB16 [0x00000000:0x00007FFF]
        BUS_BLOCK
            bank[0].BRAM [31:30];
            bank[1].BRAM [29:28];
            bank[2].BRAM [27:26];
            bank[3].BRAM [25:24];
            bank[4].BRAM [23:22];
            bank[5].BRAM [21:20];
            bank[6].BRAM [19:18];
            bank[7].BRAM [17:16];
            bank[8].BRAM [15:14];
            bank[9].BRAM [13:12];
            bank[10].BRAM [11:10];
            bank[11].BRAM [9:8];
            bank[12].BRAM [7:6];
            bank[13].BRAM [5:4];
            bank[14].BRAM [3:2];
            bank[15].BRAM [1:0];
        END_BUS_BLOCK;
    END_ADDRESS_SPACE;

END_ADDRESS_MAP;

now i re-imp with -bm auto.bmm, i get error :

Processing BMM file ...
ERROR:NgdBuild:989 - Failed to process BMM information auto.bmm

and my top level vhdl source

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity Memory is
port (
CLK : in std_logic;

  ROM_WE   : in std_logic;
  ROM_EN   : in std_logic;
  ROM_ADDR : in std_logic_vector(12 downto 0);
  ROM_DIN : in std_logic_vector(31 downto 0);
  ROM_DOUT : out std_logic_vector(31 downto 0);

  RAM_WE   : in std_logic;
  RAM_EN   : in std_logic;
  RAM_BE : in std_logic_vector(3 downto 0);
  RAM_ADDR : in std_logic_vector(12 downto 0);
  RAM_DIN : in std_logic_vector(31 downto 0);
  RAM_DOUT : out std_logic_vector(31 downto 0)
  );
end Memory;

architecture Behavioral of Memory is

signal WEB : std_logic_vector(3 downto 0);

begin
WEB(0) <= RAM_WE and RAM_BE(0);
WEB(1) <= RAM_WE and RAM_BE(1);
WEB(2) <= RAM_WE and RAM_BE(2);
WEB(3) <= RAM_WE and RAM_BE(3);

BANK : for i in 0 to 15 generate
begin

  BRAM : RAMB16_S2_S2
  generic map (

    INIT_A => X"0",         -- Value of output RAM registers on Port A at startup
    INIT_B => X"0",         -- Value of output RAM registers on Port B at startup

    SRVAL_A => X"0",         -- Port A ouput value upon SSR assertion
    SRVAL_B => X"0",         -- Port B ouput value upon SSR assertion

    WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE

    SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"

    -- The following INIT_xx declarations specify the initial contents of the RAM

    -- Address 0 to 2047
    INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Address 2048 to 4095
    INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Address 4096 to 6143
    INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Address 6143 to 8191
    INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")

  port map (

    DOA => ROM_DOUT(i*2+1 downto i*2+0),
    DOB => RAM_DOUT(i*2+1 downto i*2+0),

    DIA => ROM_DIN(i*2+1 downto i*2+0),
    DIB => RAM_DIN(i*2+1 downto i*2+0),

    ADDRA => ROM_ADDR,
    ADDRB => RAM_ADDR,

    SSRA => '0',
    SSRB => '0',

    CLKA => CLK,
    CLKB => CLK,

    WEA => ROM_WE,
    WEB => WEB(i/4),

    ENA => ROM_EN,
    ENB => RAM_EN
  );

end generate BANK;

end Behavioral;

i use 16 BRAMs to make width:32 and depth:8192 Dual Port RAM.

every BRAM is 8192 * 2, with all brams i get 8192 * 32 RAM

one port uses MCU ROM, other port uses MCU RAM.

how can i make right .bmm file now ?

fpga is XC3S400A

thank you for suggestion.

shangdawei@gmail.com · ‎01-05-2010

even if use memory/....., it is error yet.

Processing BMM file ...
ERROR:NgdBuild:989 - Failed to process BMM information auto.bmm

//////////////////////////////////////////////////////////////////////////////
//
// Processor 'MYPPC', ID 0, memory map.
//
///////////////////////////////////////////////////////////////////////////////

ADDRESS_MAP MYPPC PPC405 0

    ///////////////////////////////////////////////////////////////////////////////
    //
    // Processor 'MYPPC' address space 'ROM' 0x00000000:0x00007FFF (32 KBytes).
    //
    ///////////////////////////////////////////////////////////////////////////////

    ADDRESS_SPACE ROM RAMB16 [0x00000000:0x00007FFF]
        BUS_BLOCK
            Memory/bank[0].BRAM [31:30];
            Memory/bank[1].BRAM [29:28];
            Memory/bank[2].BRAM [27:26];
            Memory/bank[3].BRAM [25:24];
            Memory/bank[4].BRAM [23:22];
            Memory/bank[5].BRAM [21:20];
            Memory/bank[6].BRAM [19:18];
            Memory/bank[7].BRAM [17:16];
            Memory/bank[8].BRAM [15:14];
            Memory/bank[9].BRAM [13:12];
            Memory/bank[10].BRAM [11:10];
            Memory/bank[11].BRAM [9:8];
            Memory/bank[12].BRAM [7:6];
            Memory/bank[13].BRAM [5:4];
            Memory/bank[14].BRAM [3:2];
            Memory/bank[15].BRAM [1:0];
        END_BUS_BLOCK;
    END_ADDRESS_SPACE;

END_ADDRESS_MAP;

Message Edited by shangdawei@gmail.com on 01-05-2010 04:16 AM

shangdawei@gmail.com · ‎01-05-2010

RTL viewer

pavithra · ‎03-18-2010

hi i have use bram to my program but i dont have any idea please can u suggest ant doumentation or tutorial having example using bram

i hope u will reply