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xilinx-zhaosheng
Adventurer
Adventurer
3,054 Views
Registered: ‎04-10-2016

How to simulate the Vivado engineering IP core in system generator environment

A complete Vivado under the FPGA project (contains a lot of Vivado IP core), how to import into the system generator environment simulation

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balkris
Xilinx Employee
Xilinx Employee
3,025 Views
Registered: ‎08-01-2008

I would recommend you to create Sysgen design with using sysgen blocks. Sysgen design using the same IP from IP catalog . In case you want to import other RTL and IP catalog IPs for that you required use blackbox from sysgen block sets
Thanks and Regards
Balkrishan
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