07-05-2019 11:56 AM
We use XVC and a debug bridge in JTAG-BSCAN mode on a 7-series zynq device under vivado 2018.3. ILAs are automatically attached to an automatically generated debug hub which can be accessed from the JTAG-BSCAN bridge just fine.
However, it seems that IBERT cores are not connected to this debug hub but always end up on the hardware TAP (which is not remote-accessible). Is it possible to somehow instruct vivado (2018.3) to attach the IBERT to a specific debug hub? Or are there other methods so that IBERT can be accessed via XVC?
Thanks for any pointers
08-06-2019 02:02 PM
I believe you'd need to use the In-System IBERT (ISI) core for that. The regular IBERT core will be "hardwired" to the regular JTAG tap.
In fact, you are not supposed to modify an IBERT design at all. For integrating such features in a custom design, the ISI should be used.
08-06-2019 07:44 PM
Thanks for your reply.
Where do I find this 'in-system IBERT (ISI)' ? In the IP catalog (e.g., for a 7-series device) I only find one IBERT (in case of the device I'm looking at it is (under vivado 2018.3): xilinx.com:ip:ibert_7series_gtx:3.0. And this is the one I have the impression is 'hardwired' to the JTAG TAP.
Thanks for clarifying