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bthfpgaboy
Observer
Observer
12,816 Views
Registered: ‎05-03-2012

IBERT test between two boards?

I have two boards and I did make the IBERT design to test the connection in each board. There is no error in each board selftest. After that, I plan to use IBERT design to testthe connection between the two boards. I implement IBERT in the two boards and one side transmits and the other side receives. The two IBERT designs are set same. But the are errors in each side. What's wrong? reference clk? PCB design?

 

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7 Replies
bthfpgaboy
Observer
Observer
12,796 Views
Registered: ‎05-03-2012

In addition, the referenceclk is 125MHz, and line rate is 3.125Gbps

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athandr
Xilinx Employee
Xilinx Employee
12,789 Views
Registered: ‎07-31-2012

Hi,

 

Which loopback mode are you testing?

 

When you interface FPGA1 and FPGA2, you need to enable FAR end loopback mode in FPGA2 and none looback mode in FPGA1?

 

let me know if you are not doing this.

 

 

 

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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bthfpgaboy
Observer
Observer
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Registered: ‎05-03-2012

Tanks athandr,

    

Yes, I enable none loopback mode in the two FPGAs, does that matter? And what should I do?

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athandr
Xilinx Employee
Xilinx Employee
12,760 Views
Registered: ‎07-31-2012

Hi,

 

Consider FPGA 1 interfacing with FPGA2. 

 

1) Put FPGA1 in None Mode. You should be observing the IBERT core for this FPGA1 in chipscope.

2) Put the FPGA2 in "Near End" or "Far End" loopback mode.

3) In this mode, the IBERT in FPGA1 generates the prbs pattern, outputs it through TX FPGA1 -> RX FPGA2 -> LOOPBACK THROUGH PMA/PCS -> TX FPGA2 -> back to RX FPGA2 -> received in the fabric and then compared with the sent prbs pattern. 

 

Now if the TX matches with RX, the IBERT in FPGA1 shows link-up.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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bthfpgaboy
Observer
Observer
12,747 Views
Registered: ‎05-03-2012

Hi 

 

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venkata
Moderator
Moderator
12,657 Views
Registered: ‎02-16-2010

Please remember to mention the details below to give good suggestions.
1. Device used in the design
2. Design tool version
3. Medium (SFP, SMA etc) between the two boards for this current question.

When you test in one board, do you test with external cable loopback?

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akshay_acharya
Observer
Observer
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Registered: ‎10-11-2018

If we loopback at the FPGA2 in Near end PCS/PMA . Then in FPGA2 pattern generator is looped back to pattern checker of FPGA2 , hence it shows link up. Hence the FPGA1 transmitted data is not checked in FPGA2. I think this is not the valid result.

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