10-29-2014 01:45 AM
I have two boards and I did make the IBERT design to test the connection in each board. There is no error in each board selftest. After that, I plan to use IBERT design to testthe connection between the two boards. I implement IBERT in the two boards and one side transmits and the other side receives. The two IBERT designs are set same. But the are errors in each side. What's wrong? reference clk? PCB design?
10-29-2014 09:33 PM
Which loopback mode are you testing?
When you interface FPGA1 and FPGA2, you need to enable FAR end loopback mode in FPGA2 and none looback mode in FPGA1?
let me know if you are not doing this.
10-30-2014 10:04 PM
Consider FPGA 1 interfacing with FPGA2.
1) Put FPGA1 in None Mode. You should be observing the IBERT core for this FPGA1 in chipscope.
2) Put the FPGA2 in "Near End" or "Far End" loopback mode.
3) In this mode, the IBERT in FPGA1 generates the prbs pattern, outputs it through TX FPGA1 -> RX FPGA2 -> LOOPBACK THROUGH PMA/PCS -> TX FPGA2 -> back to RX FPGA2 -> received in the fabric and then compared with the sent prbs pattern.
Now if the TX matches with RX, the IBERT in FPGA1 shows link-up.
10-31-2014 01:47 AM
I implemented IBERT design in two FPGAs as you said, but the error rate is 10-4. Is this because of the reference clk,or PCB layout? There is no error if I implement IBERT in one board.
11-07-2014 03:32 AM
02-04-2019 05:09 AM
If we loopback at the FPGA2 in Near end PCS/PMA . Then in FPGA2 pattern generator is looped back to pattern checker of FPGA2 , hence it shows link up. Hence the FPGA1 transmitted data is not checked in FPGA2. I think this is not the valid result.