UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer bthfpgaboy
Observer
12,148 Views
Registered: ‎05-03-2012

IBERT test between two boards?

I have two boards and I did make the IBERT design to test the connection in each board. There is no error in each board selftest. After that, I plan to use IBERT design to testthe connection between the two boards. I implement IBERT in the two boards and one side transmits and the other side receives. The two IBERT designs are set same. But the are errors in each side. What's wrong? reference clk? PCB design?

 

0 Kudos
7 Replies
Observer bthfpgaboy
Observer
12,128 Views
Registered: ‎05-03-2012

Re: IBERT test between two boards?

In addition, the referenceclk is 125MHz, and line rate is 3.125Gbps

0 Kudos
Xilinx Employee
Xilinx Employee
12,121 Views
Registered: ‎07-31-2012

Re: IBERT test between two boards?

Hi,

 

Which loopback mode are you testing?

 

When you interface FPGA1 and FPGA2, you need to enable FAR end loopback mode in FPGA2 and none looback mode in FPGA1?

 

let me know if you are not doing this.

 

 

 

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Observer bthfpgaboy
Observer
12,102 Views
Registered: ‎05-03-2012

Re: IBERT test between two boards?

Tanks athandr,

    

Yes, I enable none loopback mode in the two FPGAs, does that matter? And what should I do?

0 Kudos
Xilinx Employee
Xilinx Employee
12,092 Views
Registered: ‎07-31-2012

Re: IBERT test between two boards?

Hi,

 

Consider FPGA 1 interfacing with FPGA2. 

 

1) Put FPGA1 in None Mode. You should be observing the IBERT core for this FPGA1 in chipscope.

2) Put the FPGA2 in "Near End" or "Far End" loopback mode.

3) In this mode, the IBERT in FPGA1 generates the prbs pattern, outputs it through TX FPGA1 -> RX FPGA2 -> LOOPBACK THROUGH PMA/PCS -> TX FPGA2 -> back to RX FPGA2 -> received in the fabric and then compared with the sent prbs pattern. 

 

Now if the TX matches with RX, the IBERT in FPGA1 shows link-up.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Observer bthfpgaboy
Observer
12,079 Views
Registered: ‎05-03-2012

Re: IBERT test between two boards?

Hi 

 

0 Kudos
Moderator
Moderator
11,989 Views
Registered: ‎02-16-2010

Re: IBERT test between two boards?

Please remember to mention the details below to give good suggestions.
1. Device used in the design
2. Design tool version
3. Medium (SFP, SMA etc) between the two boards for this current question.

When you test in one board, do you test with external cable loopback?

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Observer akshay_acharya
Observer
754 Views
Registered: ‎10-11-2018

Re: IBERT test between two boards?

If we loopback at the FPGA2 in Near end PCS/PMA . Then in FPGA2 pattern generator is looped back to pattern checker of FPGA2 , hence it shows link up. Hence the FPGA1 transmitted data is not checked in FPGA2. I think this is not the valid result.

0 Kudos