UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
309 Views
Registered: ‎04-22-2019

ILA_DEBUGGING OF BIPOLAR SIGNAL

Hi everyone,

    I got the result for XADC , I applied a continuous sine wave signal to the dedicated pin Vp and Vn. I have debugged the value.

I noticed the result is from 0000h to 7fffh only, but my input signal is from 0 to 1V , with 500 mv Vn offset

I have attached the ILA window also, what could be the reason for my output only from 0 to 0.5V 

Fig: 1 ---Interface, channel, timing mode and DCLK freq

image.png.c42c593d216e673d1533c1bfef4af04c.png

 Fig: 2 ---Bipolar Enabling

image.png.1c58679cc857dfebe9c7125d4e33739e.png

Fig: 3 ---- ILA Window

image.png.f9e8beacf1ec1ff738f97c0d262a4190.png

image.png

0 Kudos
2 Replies
Moderator
Moderator
263 Views
Registered: ‎02-09-2017

Re: ILA_DEBUGGING OF BIPOLAR SIGNAL

Hi @revathishizuoka3,

 

Would you please repost the images from your previous post? None of them have been correclt uploaded so we can't see it. That would greatly help us in understanding and debugging the issue.

Thanks,

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
238 Views
Registered: ‎04-22-2019

Re: ILA_DEBUGGING OF BIPOLAR SIGNAL

Hi ,

  Sorry for the error in images.I will upload again

I have attached my unipolar xadc output signal. Kindly check it off, the same deformation of voltage is there.

1) UNIPOLAR MODE : Vp sinput signal is 0 to 1V, with offset of 500mV.

Vn is from DAC B, default value is 0V.

Freq from generator is 10Khz

I don't understand why there is only 0.93V max and 0.3V minimum.

 

 

2) If I reduce the frequency , the ADC code gets increases like this. But its really look no meaning how it happens, why there is a indirect proportional to frequency and voltage. It may be due to any anti aliasing filter effects. I don't know exactly.

   If it is due to the low pass filter, how to reduce it. At final stage my input to the ADC will be a high frequency signal. So it is neccessary to reduce the effect.

 

I ahve atatched the XADC  output for various input frequency. 

 

 

 

unipolar xadc output.png
Bipolar xadc output.png
Comparison of frequency.png
0 Kudos