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Observer nicolas
Observer
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Registered: ‎04-26-2019

ILA Synthesis: [Opt 31-2] Missing connection on D pin

Hi,

I have one block design with a microblaze, all my design is in the block design composed of xilinx IPs. I want to transfert the streaming data from axi traffic generator to the DDR3 memory throught an axi dma ip (stream to memory mapped).

I succed to start traffic generator from sdk and i succed to probe AXI stream bus at the output of axi traffic generator. But when I want to read DDR3 with microblaze I can't see the samples generated by the etraffic generator.

So i have added a probe at the output of axi dma but this cause the implementation to fail with this error:

[Opt 31-2] SRL16E design_1_i/system_ila_0/U0/ila_lib/U0/ila_core_inst/shifted_data_in_reg[7][518]_srl8 is missing a connection on D pin.

ILA IP has been connected throught the connection automation tool in block design.

I already checked the AR# 65931 but the "select_objects [get_nets -filter {MARK_DEBUG == TRUE && ROUTE_STATUS == NOLOADS}]" command report nothing.

I am using Vivado 2019.1.1

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Moderator
Moderator
154 Views
Registered: ‎02-09-2017

Re: ILA Synthesis: [Opt 31-2] Missing connection on D pin

Hi @nicolas,

 

Could you show a screen shot of where the ILA has been placed? If you have connected the ILA to an FPGA input/output pin, it most likely won't work because that's an ILA limitation.

Just to verify, the command select_objects [get_nets -filter {MARK_DEBUG == TRUE && ROUTE_STATUS == NOLOADS}] will only work if you have the synthesized or implemented design open.

In addition, maybe you have not marked the nets with MARK_DEBUG, so could you please try running the following alternative command:

select_objects [get_nets -filter {ROUTE_STATUS == NOLOADS}]

This should bring up all the nets with no loads.

Thanks,

Andre Guerrero

Product Applications Engineer

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