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Explorer
Explorer
1,043 Views
Registered: ‎03-22-2016

ILA capture without a free-running clock

From what I can tell, ILAs need to be captured with a "free-running" clock, meaning that the clock starts up on its own when the board is programmed. If you try to use a clock that is not free-running, you may see the error "ila core clock has stopped. Unable to arm ILA core." (though, it seems to sometimes work)

My question - how can I use an ILA to capture data that is not on a free-running clock? In my case, I have a clock chip that is configured and started with microblaze. Initialization isn't fast enough to count as free-running. But the data itself is clocked at that rate, so sampling it on any other clock wouldn't be useful.

Do I need to clock-cross the data and sample that? (and deal with a valid bit) Or is there perhaps some trick to getting an ILA to work with a clock that uses the non-free-running clock as a reference? Thanks!

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

Your right

 

The ILA is simplisticly a big state machine, so it needs a clock that is constantly available,

  does the micorblaze not have a clock input which you could then use in the ILA ?

all outputs of the microblaze are syncronous to its input clock, so should be able to be captured.

 

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Explorer
Explorer
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


does the micorblaze not have a clock input which you could then use in the ILA ?

all outputs of the microblaze are syncronous to its input clock, so should be able to be captured.


The microblaze it just being used to set registers on a clock generator IC on an FMC ADC module. That clock generator provides the sample clock for the ADC and the JESD core clock. The data stream coming out of the JESD204B IP block is synchronous to that JESD core clock, but not related to the microblaze clock at all.

At the moment, I'm generating a clock that is slightly faster than the JESD core clock, but using the system clock on the board as the reference so that it will be free-running. I'm clock-crossing the data up to that faster clock and putting the ILA on the output of that FIFO. It works ok, I'm just wondering if that's what everyone else is doing, or if there's a trick I'm missing. This design will be really difficult to work with if I can't put an ILA on anything running on my data clock.

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

Im confused,
can you supply a diagram please,
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Explorer
Explorer
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock

Not sure a diagram will help, but I drew a simplified one up. The blue dotted border surrounds the FPGA design. Boxes outside that are physical hardware. The blue lines are the ADC sample clock, generated by the FMC module (not free-running). The yellow lines are a clock that is provided by the FPGA dev board (free-running). The green lines are the ADC sample data. The orange lines are SPI configuration connections to the ICs on the FMC.

Physical device (FMC module) contains a clock generator IC (HMC7044) and an ADC (AD9208). The clock is set up via register writes from microblaze (SPI). Once set up, it generates the sample clock for the ADC. That sample clock is also supplied to the FPGA as the gigabit transceiver reference clock. The ADC data is supplied to the FPGA on the gigabit transceiver lanes (JESD204B).

The FPGA design is a JESD204B core that takes in those gigabit transceiver lanes (and associated clock) and outputs decoded ADC data. That ADC data is aligned to that generated clock (40x slower, but with the same reference).

Summary: The ADC data is synchronous only to the sample clock, which is generated by an IC on the FMC module with the ADC and is not free-running, and cannot be used with an ILA as far as I know. To get around this, I am clock-crossing the ADC data and then connecting that FIFO to an ILA. I'm trying to find out if that approach is necessary or if there's some other (better) way to use an ILA with data that is synchronous to a non free-running clock.

external_clock_diagram.png
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Registered: ‎09-17-2018

Re: ILA capture without a free-running clock

ILA

requires the clock (synchronous) to capture the data.  Must be the same clock used in the logic being monitored.

If you have another clock domain, you require another ILA instantiated in that clock domain (running off that lock).

Too many clock sources will mean multiple ILA cores, which gets ugly (and makes it difficult to place and route, meet timing.

l.e.o..

 

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Explorer
Explorer
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


@lowearthorbit wrote:

ILA requires the clock (synchronous) to capture the data.  Must be the same clock used in the logic being monitored.

Yes, I understand. The problem here is that the only clock that is synchronous to the logic I am monitoring is not free-running, and therefore cannot be used with an ILA.

If you have another clock domain, you require another ILA instantiated in that clock domain (running off that lock).


Yes. I am only trying to instantiate one ILA, for one clock domain. The problem is, that clock domain uses a clock that is not free-running, and therefore cannot be used with an ILA. I'm looking for suggestions on what I can do instead.

Currently, I am crossing my data over to a different clock domain that is free-running.By "crossing over", I mean that I am using a FIFO with asynchronous clocks, I'm not just using the wrong clock to sample it. I am just trying to find out if that is what is commonly done when you want to capture data that is not synchronous to a free-running clock.


Too many clock sources will mean multiple ILA cores, which gets ugly (and makes it difficult to place and route, meet timing.

Yep, certainly. Not a problem I'm experiencing or asking about, though :-)

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

Re the fifos with free running clocks,

These fifo's need constant clocks into them,  its teh read / write lines that are gated,

     you can not use a gated clock into the fifo, else the state machines get 'confused'.

I think the ILA uses said fifo,

 

 

 

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

Just seen your diagram,

  perfect.

 

If I rember, and I can't chekc at present, the JESD cores output data via a fifo,

     i.e. they have a constant clock going into them that the output data is sent out on, with a valid.

       that should be perfect for the LA core, use th esame clock, the enable and the data .

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Voyager
Voyager
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Registered: ‎03-28-2016

Re: ILA capture without a free-running clock

One option would be to add an MMCM to your design.  Use your external clock as the input clock to the MMCM.  Set the MMCM to generate the same frequency as the input.  Use the "locked" pin on the MMCM as a reset for the logic.  That way the ILA will only see the clock once it is stable.  If you use the generated clock as your system clock, then you will have to make sure that the MMCM is phase locked to the input clock or you will have to do some sort of clock domain crossing.  Alternatley, you could use input clock a the system clock and only use the MMCM for it's locked pin.

I have used the ILAs with clocks that were not free-running.  I had to wait for the clocks to be stable before intiating any activity on the ILA.  Even then it can be a little flaky.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Explorer
Explorer
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


If I rember, and I can't chekc at present, the JESD cores output data via a fifo,

     i.e. they have a constant clock going into them that the output data is sent out on, with a valid.

       that should be perfect for the LA core, use th esame clock, the enable and the data .


That was the first thing I tried. But like I've been explaining, that clock isn't free running and doesn't work with an ILA.


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Explorer
Explorer
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


@tedbooth wrote:

One option would be to add an MMCM to your design.  Use your external clock as the input clock to the MMCM.  Set the MMCM to generate the same frequency as the input.  Use the "locked" pin on the MMCM as a reset for the logic.  That way the ILA will only see the clock once it is stable.  If you use the generated clock as your system clock, then you will have to make sure that the MMCM is phase locked to the input clock or you will have to do some sort of clock domain crossing.  Alternatley, you could use input clock a the system clock and only use the MMCM for it's locked pin.

I have used the ILAs with clocks that were not free-running.  I had to wait for the clocks to be stable before intiating any activity on the ILA.  Even then it can be a little flaky.


That sounds promising, I'll give that a try, thanks! If I'm reading you right, if I hold the ILA in reset until the clock is stable, it might work fine? I'm now thinking that my reset block for that clock isn't correct, and that might be the real root of the problem if brings the ILA out of reset before the clock is actually enabled.

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

The clock into the JESD block, from the fabric, on which the data out of the JESD to the fabric is not free running ?

   you might want to check thats ok,

at the least . hold the JESD block in reset till the clock into it is stable,

 

 

 

 

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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


@drjohnsmith wrote:

The clock into the JESD block, from the fabric, on which the data out of the JESD to the fabric is not free running ?


The clock into the JESD block is not from the fabric. It is from an external physical device and it is not free running. The JESD block is designed for that and works fine. It's only the ILA that has a problem with non free-running clocks.

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

My apologies, I have used three different JESD cores, all have clocks into them from the fabric for data transferred between the core and the fabric. They have other clocks for the serial link , which is from outside the fabric.

Is this a core of your own or can we know which it is please,
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


@drjohnsmith wrote:
My apologies, I have used three different JESD cores, all have clocks into them from the fabric for data transferred between the core and the fabric. They have other clocks for the serial link , which is from outside the fabric.

Is this a core of your own or can we know which it is please,

This is the Xilinx JESD204 IP core. 

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: ILA capture without a free-running clock

The Xilinx JESD 7.2 core has an AXI stream interface with the fabric,

This interface runs at the fabric clock you send to the core,

      ( Rx_core_clk or Tx_Core_clk )

which are constant clocks,

so data out of the core can be grabed on these fabric clocks ,

 unless I'm miss understanding totaly

 

 

 

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Explorer
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Registered: ‎03-22-2016

Re: ILA capture without a free-running clock


@drjohnsmith wrote:

The Xilinx JESD 7.2 core has an AXI stream interface with the fabric,

This interface runs at the fabric clock you send to the core,

      ( Rx_core_clk or Tx_Core_clk )

which are constant clocks,

so data out of the core can be grabed on these fabric clocks ,

 unless I'm miss understanding totaly


Those are not constant clocks. See the section "Clocking" in PG066 (page 46), specifically the diagrams on where the core and reference clocks are generated.

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