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Explorer
Explorer
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Registered: ‎05-31-2017

ILA don't display probes

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Hi everybody,

 

I am now in the debug step.

I make a little project with following the xapp1097 (SDI Rx and Tx, I only need Rx).

When I try to use an ILA for debug, I reach the final step (device programing) but in the ILA dashboard there is nothing...

 

During "Set Up Debug", is it recommanded to use the clock domain automaticaly choose by Vivado or select a free running clock (27MHz, slower)?

 

Nothing works for me.

 

I checked the Timing report : OK

I tried to decrease the JTAG frequency : no result.

In the ILA properties > STATIC > ILA_FREQUENCY = 0 .

 

I can upload the code if somebody wants to inspect it.

 

Thank you

 

Paul

 

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Moderator
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Registered: ‎07-01-2015

Re: ILA don't display probes

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Hi @pgrangeray,

 

Can you please click on + sign and see if the probes are available?

Thanks,
Arpan
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Mentor
Mentor
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Registered: ‎02-24-2014

Re: ILA don't display probes

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Did you get an LTX file when you generated the ILA debug logic?     It's usually called  "debug_nets.ltx" and is an XML file that tells Vivado Debugger the names of all the signals being monitored by the ILA core.   This needs to be loaded into the hardware manager when you are connecting to the target device via JTAG.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
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Registered: ‎10-19-2011

Re: ILA don't display probes

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What is the ila clock being driven by? Is that source free running? Free running meaning, that is is available at the startup of the FPGA. If there is a delay or setup time associated with the clock then that is likely the problem. If you right click on the ila in the hw manager window and select refresh, does this get the ILA re-connected? I have seen some situations were this can work around the non free running clock. However there are limitations to what the refresh can work around. There is a state machine that needs a clock when the FPGA starts up to get the ILA connected and synced. 

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Explorer
Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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I have a top.ltx (my top is top.vhd) and debug_probes.ltx.

Is it normal? I used to choose top.ltx.

 

I read both files and code is the same.

 

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Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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HI @travisc

 

I tried with a free running clock and other clock.

This morning I managed to get a probe...

 

My clock is an output of a BUFG (connected to an external oscillator). 

 

I can run ILA multiple times, but without probes.

 

The CORE_UUID is "000000000000000000000000000000000". Is it a problem?

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Registered: ‎09-15-2016

Re: ILA don't display probes

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Hi @pgrangeray

 

In addition to the @travisc suggestions can you please make sure that your JTAG frequency is half to the ILA frequency? Refer the below link, chapter 4:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug908-vivado-programming-debugging.pdf

 

Regards

Rohit

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Regards
Rohit
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Explorer
Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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Hi @thakurr

 

The ILA is 27MHz, and the JATG cable clock is 1 MHz.

 

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Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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I have just seen this warning (bitstream generation ok): 

 

[DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/s_bscan_tms, u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[13], u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[14], u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[15], u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[16]... and (the first 15 of 19 listed).

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Moderator
Moderator
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Registered: ‎10-19-2011

Re: ILA don't display probes

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When you say you were able to get a probe, what exactly does that mean? Are you using a custom board or one of our dev kits? What was the exact change the made the behavior of the probe different, (i assume the clock, but wanted to check as it isnt very clear)? Can you also clarify what you mean by running multiple times but without probes? Are you referring to your design or are you able to run some form of ILA capture but you arent seeing any data?
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Explorer
Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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@travisc

 

I can't remember what i've changed... Clock for sure, some constraints maybe. The level where I place th ILA ( top module, or sub module).

It is a custom board.

I can run the capture in the ILA, but no probe (or line) is displayed on the dashboard (like if there is no probe).

I will make a screenshot tomorrow.

 

 

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Explorer
Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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I make the ILA with the synth schematic (Mark debug, and setup debug).

 

You will find attached some screenschots. 

 

I've tried with Vivado 2017.3.1 and 2017.4, it is the same.

 

 

Warning message during bitstream generation :

 

[DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/s_bscan_tms, u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[13], u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[14], u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[15], u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[16]... and (the first 15 of 19 listed).

 

 

Thanks to you

impl_schem.JPG
synth_design.JPG
ILA.JPG
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Moderator
Moderator
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Registered: ‎07-01-2015

Re: ILA don't display probes

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Hi @pgrangeray,

 

Can you please click on + sign and see if the probes are available?

Thanks,
Arpan
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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Explorer
Explorer
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Registered: ‎05-31-2017

Re: ILA don't display probes

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OK,

 

SO @arpansur , i'm a stupid!

By clicking on the "+" I can add probes...

I tried the "+" in the trigger window but not this one... 

I lost almost 2 days with this crap !!

 

Thanks everybody!

 

I hope one day i will help!

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Contributor
Contributor
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Registered: ‎08-18-2017

Re: ILA don't display probes

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VERY glad I stumbled across this thread!  I also wasted almost 2 days with the same issue.  What fooled me was that I had previously implemented 4 other ILAs in my design, and they all populated the probes automatically when I launched the HW manager.  Then I added a 5th ILA, and it had no probes.  I tried reusing the same ILA IP as my previous probes, removing and adding other ILAs, and at some point the probes weren't even showing up in ILAs where they previously had been.  It was all very confusing behavior by the GUI.  Luckily I ended up here, and sure enough, it turns out that not all ILAs automatically add all the probes to the waveform view.  Out of curiosity, is there deterministic behavior to this?  Or did my luck just change?  

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Observer
Observer
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Registered: ‎03-05-2019

Re: ILA don't display probes

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I ran into a similar issue with Vivado 2019.2. I added two ILA cores to my design. One of them automatically populated all of the probes, and the other didn't, despite them having nearly identical setups. Quite unexpected, but an easy fix (once I found this thread).

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