When the error says "Free running" it means un-gated. Are you sure that the PLL is outputting the clock? Could it be held in reset? Often axi resets are asserted low, and the PLL's reset may be asserted high. An easy check is to pipe the clock you are using on the ILA out a pin, and check with a scope. Also, check your post-synth schematic and ensure the clock is actually connected to something, and not gated in a way you do not expect.