02-08-2021 02:02 AM
i am using kintex 7 board. when adding chip scope in project , signal which i want to check is not showing in chip scope. is there any setting in ISE for show all nets in chip scope.
02-08-2021 05:42 AM
Your using a Kintex, yet you are no tusing the Vivado desing tool ?
If you want to use ISE, then at least use the last version 14.7
What is your OS, ISE 14.4 does not work on W10.
02-10-2021 11:40 PM
hi i am using window 7. my whole project on the ise14.4. if I change ise14.4 to 14.7 , will chipscope show all the netlists.
please provide me solution in ISE14.4.
02-10-2021 11:59 PM
I think you have not optimized your VHDL/verilog code. Same problem i have encountered , you just check the width of register used in code(for that particular signal).
U can give code here also community will help you