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lanxiang.ben
Participant
Participant
10,796 Views
Registered: ‎04-08-2014

Ila debug core Programmer problem

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Hi All

        How to handle this problem?

        Please examine the ancessory

BR

lanxiang

捕获.PNG
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1 Solution

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yashp
Moderator
Moderator
18,617 Views
Registered: ‎01-16-2013

Hello,

 

ILA input clock is constraint properly?

Is your design meeting all timing requirements?

 

Thanks,

Yash

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vijayak
Xilinx Employee
Xilinx Employee
10,793 Views
Registered: ‎10-24-2013

Hi,

Please check this AR

http://www.xilinx.com/support/answers/52939.html

Thanks,Vijay
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yashp
Moderator
Moderator
18,618 Views
Registered: ‎01-16-2013

Hello,

 

ILA input clock is constraint properly?

Is your design meeting all timing requirements?

 

Thanks,

Yash

View solution in original post

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vijayak
Xilinx Employee
Xilinx Employee
10,689 Views
Registered: ‎10-24-2013
Hi @lanxiang.ben Is your issue solved? Please mark that helped you as solution.
Thanks,Vijay
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xiaohu125
Contributor
Contributor
10,612 Views
Registered: ‎06-13-2014
hi,

I have fixed it by Installing vivado- v2013.2 and just slower the JTAG frequency to ensure it is slower than my ILA frequency.

But I have another question: I can not change the JTAG clock in vivado 2014.1, why ?

Thanks
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