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Visitor migname
Visitor
7,735 Views
Registered: ‎08-10-2009

Impact: TCK frequency to low

Hello,

 

I am working on a custom made board which contains a "xc5vlx50" device. The virtex is the only device in the JTAG chain. In the used bsd file (C:/Xilinx/11.1/ISE/virtex5/data/xc5vlx50.bsd) I can find a maxium tck frequency of 33Mhz for this device. The cable setting was set to 6Mhz before starting Impact. When I try to upload a bitfile to the device the TCK frequency is set down to 1Mhz.

Here the console output of Impact:

 

INFO:iMPACT:1777 -
Reading C:/Xilinx/11.1/ISE/virtex5/data/xc5vlx50.bsd...
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
INFO:iMPACT:501 - '1': Added Device xc5vlx50 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Active mode is BS
Project: 'C:/uBlaze_testsystem/ISE_Project/Impact_Setting.ipf' loaded.
'1': Loading file 'C:/uBlaze_testsystem/ISE_Project/ublaze_system.bit' ...
done.
UserID read from the bitstream file = 0xFFFFFFFF.
INFO:iMPACT:501 - '1': Added Device xc5vlx50 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
GUI --- Auto connect to cable...
AutoDetecting cable. Please wait.
PROGRESS_START - Starting Operation.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 10.0.1.0. WinDriver v10.01minor 1 Jungo (c) 1997 - 2009 Build Date: May 14 2009 X86 32bit SYS 13:42:25, version = 1001.
 Cable PID = 0008.
 Max current requested during enumeration is 300 mA.
Type = 0x0005.
 Cable Type = 3, Revision = 0.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 2401.
File version of C:/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
Firmware hex file version = 2401.
PLD file version = 200Dh.
 PLD version = 200Dh.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
INFO:iMPACT - Current time: Do 17. Feb 09:05:01 2011
PROGRESS_START - Starting Operation.
Warning: Chain frequency (1000000) is less than the current cable speed (6000000).
 Adjust to cable speed (1000000).
Maximum TCK operating frequency for this device chain: 1000000.

Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   42,01 C, Min. Reading:   28,23 C, Max. Reading:   42,01 C
1: VCCINT Supply: Current Reading:   0,999 V, Min. Reading:   0,993 V, Max. Reading:   1,014 V
1: VCCAUX Supply: Current Reading:   2,490 V, Min. Reading:   2,490 V, Max. Reading:   2,505 V
'1': Programming device...
 Match_cycle = 2.
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 1001 1110 0000 1010 1000 0000
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT - '1': Programing completed successfully.
 Match_cycle = 2.
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time =     34 sec.

 

If I try this from another pc with the same download cable and the same hardware everthing is fine and the used TCK frequency is 6Mhz. After this I can find a cable setting of 750Khz in the cable setup.

Does somebody has an idea what's going wrong here?

 

Thank you for your help.

 

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4 Replies
Xilinx Employee
Xilinx Employee
7,718 Views
Registered: ‎07-30-2007

Re: Impact: TCK frequency to low

The software is going to run a quick test on the JTAG chain and make sure the chain can run at the speed selected.  If the test fail at the speed selected the speed is derated and the test is run again.  So, it looks like the 6MHz chain integrity test was unable to run sucessfully and the speed was derated to 1MHz.  You can see this since the derating is after "PROGRESS_START - Starting Operation.". 

 

To fix this there may need to be some TCK line termination and maybe series resistors added to get the JTAG test to pass at full speed.  Also, you can upgrade your software, don't think it will change this but it is always good to stay on the latest software.

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Visitor migname
Visitor
7,667 Views
Registered: ‎08-10-2009

Re: Impact: TCK frequency to low

Thank you for your quick reply.


To find out if the integrity of the TCK signal is the problem I did the following:
- put probes of scope to TCK (yellow), TDI (green) and TMS (blue) line.
- trigger on falling edge of TCK, single shoot mode
- set cable speed to 6Mhz
- start "Chain Integrity Test" manually from the debug menu

In the console I have found the following output:

INFO:iMPACT - Current time: Do 24. Feb 11:48:08 2011
Warning: Chain frequency (1000000) is less than the current cable speed (6000000).
 Adjust to cable speed (1000000).
Maximum TCK operating frequency for this device chain: 1000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   43,98 C, Min. Reading:   28,23 C, Max. Reading:   44,96 C
1: VCCINT Supply: Current Reading:   0,996 V, Min. Reading:   0,993 V, Max. Reading:   1,005 V
1: VCCAUX Supply: Current Reading:   2,490 V, Min. Reading:   2,487 V, Max. Reading:   2,505 V

 

The scope result:

 

TCK_problem.png

From the output I can see that the platform cable is in "6 Mhz mode" but I'am wondering why the first clock cycle of the TCK signal is already set to the frequency of 750Khz at the beginning of this test.
Do you have any further ideas how this could happen?

Best regards

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Xilinx Employee
Xilinx Employee
7,658 Views
Registered: ‎07-30-2007

Re: Impact: TCK frequency to low

It looks like impact is runnign the chain integrity testing as slow speeds first. 

 

If you have a system that will run at 6MHz you should be able to see the increased frequency during downloading.  You can also see the download time reduced with the increased frequncies in the log. 

 

The signals all look good from what you have.  It would be best to get a zoomed in scope shot of the rising edge of TCK to check for reflections at the TCK pin of the FPGA. 

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Observer renearts
Observer
5,282 Views
Registered: ‎11-28-2013

Re: Impact: TCK frequency to low

Hey everyone,

 

Took a while :+) , but I found a solution to this problem! 

Yesterday I found a solution to another problem which I think is related. I was unable to generate some IP cores directly from my projects in ISE. I had to open the core generator from the Tools menu, then generate a core and add it manually to my project.

This was caused by a different numeric locale setting. Default at my pc (running Ubuntu 14.04, ISE 14.7 lin64) is nl_NL.UTF-8. The case seems that ISE expects en_US.UTF-8, so it interprets '.' as ',' and vice versa. During the generation of the cores it would stop and give a quite undiscriptive error. After an extensive search I found the problem cause to be the locale setting wich I fixed adding the third and fourth line to my ISE startup script:

 


 

#!/bin/bash
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
LC_NUMERIC=en_US.UTF-8
export LC_NUMERIC
ise


 

 

Skipping back to a few minutes ago; I was programming my FPGA and noticed it was way faster than before. At first I thought something went wrong (couldn't believe it was done in 20secs instead of +2min) and tried again with the same result, though the FPGA seemed to work as expected. 

After examining the Impact console log I found the chain speed warning had disappeared. Removing the lines from the startup script let everything get slow again. 

I guess Xilinx is using some decimals somewhere in the communication or configuration files :-)

Happy flashing!