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333 Views
Registered: ‎11-02-2019

Increase Sample Data Depth in System ILA

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Hi!

I have done a design in Vivado 2019.1 for the Zynq ZCU102 board. I want to debug it with a bigger Sample Data Depth, but when I try to increase it in the ILA block paramenters, if I select higher than 16384 I get an error:

"Validation failed for parameter 'BRAM utilization count(C_BRAM_CNT)' with value '1271.5' for BD Cell 'system_ila_0'. The maximum BRAM utilization cannot exceed 912 BRAMs in this device"

Is there something I can do to solve this?

Thank you

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miker
Xilinx Employee
Xilinx Employee
256 Views
Registered: ‎11-30-2007

alonsosara44@gmail.com 

I'm not sure which device you are targeting but this warning indicates you have run out of Block RAM (BRAM) resources which is used by the ILA to store captured data.  My guess is that there is not much you can do.  Your choices would be:

  1. Remove unnecessary logic from the design which utilizes BRAM
  2. Convert logic targeting BRAM in the design to LUTRAM (to free up BRAM resources)
  3. Populate PCB with larger FPGA (PL) density in footprint compatible package to gain access to additional BRAM resources [likely NOT an option]
Please Reply, Kudos, and Accept as Solution.

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1 Reply
miker
Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎11-30-2007

alonsosara44@gmail.com 

I'm not sure which device you are targeting but this warning indicates you have run out of Block RAM (BRAM) resources which is used by the ILA to store captured data.  My guess is that there is not much you can do.  Your choices would be:

  1. Remove unnecessary logic from the design which utilizes BRAM
  2. Convert logic targeting BRAM in the design to LUTRAM (to free up BRAM resources)
  3. Populate PCB with larger FPGA (PL) density in footprint compatible package to gain access to additional BRAM resources [likely NOT an option]
Please Reply, Kudos, and Accept as Solution.

View solution in original post