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Registered: ‎01-03-2020

Is there a way to write default I/O Std into xdc files automatically when saving IO port from scheme

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Hi,

I implemented very simple design by RTL and set IO package pin from Schematic manually.

There is also I/O std section, but I did not touch there at first because that section have already set as default.

I generated constraint file(.xdc file) and there is no description about IOSTANDARD, I got an error because of no IOSTANDARD in .xdc.
To suppress this error, I set parameters in I/O Std section manually and got description abount IOSTANDARD in .xdc file.
Errors are gone, but setting I/O Std manually is very annoying for me.

Do I need to set I/O Std section even if there is value as default?
If not, how to write IOSTANDARD default value into .xdc file?

Environment:
OS: Ubuntu 18.04 LTS
Vivado: 2019.2

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287 Views
Registered: ‎01-22-2015

@soyaohnishi 

Perhaps you are annoyed with specifying IOSTANDARD because you think it is trivial and unimportant?  If so, then you are wrong.  Setting IOSTANDARD incorrectly can damage the FPGA and can damage devices connected to the FPGA.

First, understand that FPGA IO are arranged in banks and each bank is powered by a voltage called VCCO.  The value of VCCO determines the IOSTANDARDs available to you (eg. see Table 1-55 in UG471(v1.10)).

So, plan to spend some time carefully selecting IOSTANDARD for each FPGA IO and you will be rewarded with a design that both works and is safe.

View solution in original post

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288 Views
Registered: ‎01-22-2015

@soyaohnishi 

Perhaps you are annoyed with specifying IOSTANDARD because you think it is trivial and unimportant?  If so, then you are wrong.  Setting IOSTANDARD incorrectly can damage the FPGA and can damage devices connected to the FPGA.

First, understand that FPGA IO are arranged in banks and each bank is powered by a voltage called VCCO.  The value of VCCO determines the IOSTANDARDs available to you (eg. see Table 1-55 in UG471(v1.10)).

So, plan to spend some time carefully selecting IOSTANDARD for each FPGA IO and you will be rewarded with a design that both works and is safe.

View solution in original post