08-15-2013 12:20 AM
I'm having an issue while using the Vivado logic analyzer in Vivado 2012.4.
I'm limited in the number of signals i can analyze because of systematic error of type High Utilization of BRAMs with a rate of occupency of BRAM of 7%.
The number of signal i can analyze without error depends of my design, but it is not big. Arround 100 bits in total and in some configuration much less.
I explain you the context :
I'have join a capture of the error. It says that a possible reason is high utilization of BRAM, but it says it use only 7% of the capacity. I have try many different configurations. For example with less debug signals. It works when i'm using less than 7% of the Bram.
When my design is bigger, i can add less debug signals. It's annoying because i'm trying also to debug a SOPC with two processor and i can only have a few debug signals, like two with a width of 32 bits or even less.
I have tried many things, and i'm really stuck now. Is there any solution.
If you need more informations, i would be glad to give them to you.
I'm looking to your answer.
08-15-2013 01:28 AM
Can you post the synthesis utilization report?
From the error it looks like the tool is running short of BRAM resources. Can you try below:
If you are inferring RAM in the HDL, try applying the RAM_STYLE attribute as DISTRIBUTED in HDL. Refer to page-36 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug901-vivado-synthesis.pdf for syntax details.
You can try to use the switch -ram_style distributed switch in more options field in synthesis properties.
This can free up the BRAM resources for the storage purpose(logic analyzer).
08-16-2013 02:21 AM
Thank you for your quick answer. I join the utilization report after the synthesis of my design (reportUtilization.txt). For me everything looks ok.
I have tried to use the switch -ram_style distributed. I wrote -ram_style distributed in the option case of the synthesis properties. Is that right? Because nothing changed. I have exactely the same Utilization report (reportUtilization_switchram-style-distrib.txt)
I have a question. Theses utilization report are only of the synthesis of my design but without the debug core that i'm adding. Is it possible to have it also with the debug core included? Because when i re-run the synthesis, it takes off my debug block.
I join you again the capture of the error of the run i did for the utilization report.