UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor miripli
Visitor
9,904 Views
Registered: ‎08-15-2013

Issue with the Vivado logic analyser - limited in the number of signals i can analyze

Hi,

 

I'm having an issue while using the Vivado logic analyzer in Vivado 2012.4.

I'm limited in the number of signals i can analyze because of systematic error of type High Utilization of BRAMs with a rate of occupency of BRAM of 7%.

The number of signal i can analyze without error depends of my design, but it is not big. Arround 100 bits in total and in some configuration much less.

 

I explain you the context :

 

  1. I'm using a Xilinx Virtex-7 FPGA VC707 Evaluation Kit
  2. The design I'm loading is a SOPC configured from the GRLIB provided by Aeroflex Gaisler. There is one processor, one Amba Bus, a UART, a memory Ctrl and a few other ctrl
  3. I'm using the Vivado 2012.4 GUI
  4. The design works well without adding blocks from the debug analyzer 
  5. I try then to debug with the Vivado logic analyzer
  6. I add signals by adding mark_debug attribute to my VHDL files
  7. I synthesize  then my design
  8. I open then the debug View tab
  9. I click through the wizard to create a Vivado logic analyzer debug core with the signal I want.
  10. When the ILA cores are created, I run the implementation. And it's here the error appears.

 

I'have join a capture of the error. It says that a possible reason is high utilization of BRAM, but it says it use only 7% of the capacity. I have try many different configurations. For example with less debug signals. It works when i'm using less than 7% of the Bram.

When my design is bigger, i can add less debug signals. It's annoying because i'm trying also to debug a SOPC with two processor and i can only have a few debug signals, like two with a width of 32 bits or even less.

 

I have tried many things, and i'm really stuck now. Is there any solution.

If you need more informations, i would be glad to give them to you.

 

I'm looking to your answer.

vivado_bram_issue.JPG
0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
9,898 Views
Registered: ‎09-20-2012

Re: Issue with the Vivado logic analyser - limited in the number of signals i can analyze

Hi,

 

Can you post the synthesis utilization report?

 

From the error it looks like the tool is running short of BRAM resources. Can you try below:

 

If you are inferring RAM in the HDL, try applying the RAM_STYLE attribute as DISTRIBUTED in HDL. Refer to page-36 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug901-vivado-synthesis.pdf for syntax details.

 

or 

 

You can try to use the switch -ram_style distributed switch in more options field in synthesis properties. 

 

This can free up the BRAM resources for the storage purpose(logic analyzer).

 

Regards,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Visitor miripli
Visitor
9,875 Views
Registered: ‎08-15-2013

Re: Issue with the Vivado logic analyser - limited in the number of signals i can analyze

Hi,

 

Thank you for your quick answer. I join the utilization report after the synthesis of my design (reportUtilization.txt). For me everything looks ok.

 

I have tried to use the switch -ram_style distributed. I wrote -ram_style distributed in the option case of the synthesis properties. Is that right? Because nothing changed. I have exactely the same Utilization report (reportUtilization_switchram-style-distrib.txt)

 

 

I have a question. Theses utilization report are only of the synthesis of my design but without the debug core that i'm adding. Is it possible to have it also with the debug core included? Because when i re-run the synthesis, it takes off my debug block.

 

I join you again the capture of the error of the run i did for the utilization report.

 

Regards,

 

Yanick

0 Kudos